Optimized Fault-Tolerant Buffer Design for Network-on-Chip Applications

Abstract

Newest technologies of integrated circuits manufacture allow billions of transistors arranged in a single chip, which requires a communication architecture with high scalability and parallelism degree, such as a Network-on-Chip (NoC). As the technology scales down, the probability of Multiple Cell Upsets (MCUs) increases, being Error Correction Code (ECC) the most used technique to protect stored information against MCUs. NoC buffers are components that suffer from MCUs induced by diverse sources, such as radiation and electromagnetic interference.Thereby, applying ECCs in NoC buffers may come as a solution for reliability issues, although increasing the design cost and requiring a buffer with higher storage capacity. This paper proposes an optimized buffer using an Extended Hamming code to deal with MCUs and enhance the protected information storage, pursuing to reduce the area and power required for ECC implementation. We guide the optimized buffer evaluation by measuring the fault tolerance efficiency, buffer area, power overhead and performance of the proposed technique. All tests included the comparison with a non-optimal appliance of ECC in a NoC buffer. The results show the proposed technique reduces the area and power overhead in buffers with ECC and allows a considerable fault tolerance against MCUs with a small performance impact.

Optimized buffer protection for network-on-chip based on Error Correction Code

“…This work evaluates the Optimized [14] and Extended [13] buffer schemes of fault-tolerant NoC buffer architectures for applying three ECCs of different correction levels. The Optimized buffer scheme applies protection to all stored data.…”

“…This work extends our previous scheme for NoC buffer design [14] and analyses the impact of an optimized ECC model for implementing three types of ECCs on the router buffers: ExHamming [13], ExHamming with interleaving and FUEC-TAEC [15]. These router buffers are designed to store the packet flits that travel in the NoC, as well as the redundancy words generated by the encoders.…”

“…The Basic buffer scheme is a straightforward buffer implementation; the Extended buffer approach was proposed by Silva et al [13], whereas the Optimized buffer scheme was proposed in Ref. [14]. Our previous work [14] only applied the Optimized scheme for ExHamming code; here, we extend this model assessment by adding two different ECCs: Interleaved ExHamming and FUEC-TAEC codes.…”

“…[14]. Our previous work [14] only applied the Optimized scheme for ExHamming code; here, we extend this model assessment by adding two different ECCs: Interleaved ExHamming and FUEC-TAEC codes.…”

Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip Router

“…In works [11]- [13], the authors discuss the yield of vertical links in 3-D NoCs. The work [14] proposes a fault-tolerant buffer design. The studies [8], [15], and [16] examine intermittent faults and treat them as permanent faults.…”