Newest technologies of integrated circuits manufacture allow billions of transistors arranged in a single chip, which requires a communication architecture with high scalability and parallelism degree, such as a Network-on-Chip (NoC). As the technology scales down, the probability of Multiple Cell Upsets (MCUs) increases, being Error Correction Code (ECC) the most used technique to protect stored information against MCUs. NoC buffers are components that suffer from MCUs induced by diverse sources, such as radiation and electromagnetic interference.Thereby, applying ECCs in NoC buffers may come as a solution for reliability issues, although increasing the design cost and requiring a buffer with higher storage capacity. This paper proposes an optimized buffer using an Extended Hamming code to deal with MCUs and enhance the protected information storage, pursuing to reduce the area and power required for ECC implementation. We guide the optimized buffer evaluation by measuring the fault tolerance efficiency, buffer area, power overhead and performance of the proposed technique. All tests included the comparison with a non-optimal appliance of ECC in a NoC buffer. The results show the proposed technique reduces the area and power overhead in buffers with ECC and allows a considerable fault tolerance against MCUs with a small performance impact.
Each new production technology of integrated circuit (IC) drives more transistors area reduction, implying smaller and denser circuits. This scenario allows integrating several Processing Elements (PEs) into the same IC with efficient communication architecture such as the scalable topologies of Network on Chip (NoC). However, these newer production technologies introduce more defects in various parts of the IC that have to be detected and well corrected to prevent malfunction of the IC. This work presents the Fault Prediction Module (FPM), which presents low area consumption and a power circuit based on thresholds enabling to detect link quality, i.e. operating properly, operating with fault tendency or with permanent fault. Additionally, we show how to tune the FPM threshold parameter aiming to use this circuit as a mechanism with comprehensive fault model. The set of experimental results shows the effectiveness of our proposal.
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