Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip Router

Abstract

This work investigates synthesis alternatives to minimize error propagation in the controllers responsible for flow regulation, packet routing, and resource arbitration in a Network-on-Chip router. The controllers are based on Finite-State Machines to provide flexibility and favor low resource usage in programmable logic devices. The proposed router embeds hardening techniques by using triple modular redundancy on controllers and the Hamming code on buffers. Experimental results show that the packet routing controller has the most impact on the metrics evaluated and that the migration from a Moore to a Mealy controller implementation reduces the error propagation and offers a higher throughput than hardening the controllers. The main contribution of this work consists of assessing the impact of different implementations of a router in terms of error propagation.

A novel buffering fault‐tolerance approach for network on chip (NoC)

“…Following that, other research studies about fault-tolerant routers are proposed in Ref. [12,[17][18][19][20][21]. In Ref.…”

“…Routing algorithms for NoCs are discussed in Ref. [15,17,[22][23][24][25][26][27][28][29], but this study did not consider energy efficiency. However, it did not consider the study of power consumption in NoC.…”

“…In Ref. [17], which is in pursuit of Ref. [16], a method for tolerating a series of permanent and transient faults with flooding algorithms and random walk is proposed.…”

“…In Ref. [17], by distance vector routing and link status algorithms, permanent errors that happen in routers and links are tolerated. In Ref.…”