Optimized embedded memory diagnosis

Carvalho, Maurício; Bernardi, P.; Reorda, M. Sonza; Campanelli, N.; Kerekes, T.; Appello, D.; Barone, M.; Tancorre, V.; Terzi, M.

doi:10.1109/ddecs.2011.5783109

Cited by 9 publications

(2 citation statements)

References 4 publications

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“…Memory diagnosis approaches use various methods to identify and diagnose memory faults, e.g., fault pattern identification [6][7][8], fault signatures [1,9,10]. However, they hardly make any distinction between memory array faults and faults in other parts of the memory, such as decoders and peripherals.…”

Section: Introductionmentioning

confidence: 99%

Hierarchical Memory Diagnosis

Medeiros

Fieback

Gebregiorgis

et al. 2022

2022 IEEE European Test Symposium (ETS)

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High-quality memory diagnosis methodologies are critical enablers for scaled memory devices as they reduce time to market and provide valuable information regarding test escapes and customer returns. This paper presents an efficient Hierarchical Memory Diagnosis (HMD) approach that accurately diagnoses faults in the entire memory. Faults are diagnosed hierarchically; first, their location, then their nature (i.e., static or dynamic), and finally, their functional fault model. The HMD approach leads to a more accurate diagnostic, enabling the precise identification of yield loss causes.

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Section: Introductionmentioning

confidence: 99%

Hierarchical Memory Diagnosis

Medeiros

Fieback

Gebregiorgis

et al. 2022

2022 IEEE European Test Symposium (ETS)

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show abstract

“…The memory module with high density and complexity is fault-prone. A lot of works were carried out to examine the memory defects [1][2][3][4][5], but none of the work is to design lowcost memory tester.…”

Section: Introductionmentioning

confidence: 99%

VHDL Modelling of Low-CostMemory Fault Detection Tester

Chun

Leong

Yoong

et al. 2020

JETAP

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Memory modules are widely used in varies kind of electronics system design. The capacity of the memory modules has increased rapidly since the past few years in order to satisfy the high demand from the end-users. The memory modules’ manufacturers demand more units of automatic test equipment (ATE)to increase the production rate. However, the existing ATE used in the industry to carry out the memory testing is too costly(at least a million dollars per ATE tester). The low-cost memory testers are urgently needed to increase the production rate of the memory module. This has in spired us to design a low-cost memory tester. A low-cost memory fault detection tester with all the major fault detection algorithms that used in industry is modelled using Very High Speed Integrated Circuit Hardware Description Language (VHDL) in this paper to support the need of the low-cost ATE memory tester. The fault detection algorithms modelled are MATS+ (Modified Algorithm Test Sequence), MATS++, March C, March C-, March X ,March Y, zero-one and checkerboard scan tests. PERL program is used to analyse the simulation results and a log file will be generated at the end of the memory test. Extensive simulation and experimental test results show that the memory tester modelled covers all the memory test algorithms used in the industry. The low-cost memory fault detection tester designed provides the 100% fault detection coverage for all memory defects.

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An Efficient Fault Detection and Diagnosis Methodology for Volatile and Non-Volatile Memories

Martirosyan

Harutyunyan

2019

2019 Computer Science and Information Technologies (CSIT)

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Optimized embedded memory diagnosis

Cited by 9 publications

References 4 publications

Hierarchical Memory Diagnosis

Hierarchical Memory Diagnosis

VHDL Modelling of Low-CostMemory Fault Detection Tester

An Efficient Fault Detection and Diagnosis Methodology for Volatile and Non-Volatile Memories

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