Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection

Abstract

MOS-triggered silicon-controlled rectifier (SCR) devices have been reported to achieve efficient on-chip electrostatic discharge (ESD) protection in deep-submicrometer CMOS technology. The channel length of the embedded MOS transistor in the MOS-triggered SCR device dominates the trigger mechanism and current distribution to govern the trigger voltage, holding voltage, on resistance, second breakdown current, and ESD robustness of the MOS-triggered SCR device. The embedded MOS transistor in the MOS-triggered SCR device should be optimized to achieve the most efficient ESD protection in advanced CMOS technology. In addition, the layout style of the embedded MOS transistor can be adjusted to improve the MOS-triggered SCR device for ESD protection.

Design of Destruction Protection and Sustainability Low-Dropout Regulator Using an Electrostatic Discharge Protection Circuit

“…However, the proposed ESD protection circuit increased the holding voltage from 2.9 V to 5.8 V through a structural transformation of the conventional LRSCR; therefore, it is suitable for the 5 V class ESD design window and has a higher current driving capability through the excellent parallel discharge path [33,34]. In summary, since the holding voltage of the conventional LRSCR is lower than the proposed LDO regulator's maximum operating voltage of 4.5 V, a latch-up problem occurs [35]. So, even if the conventional LRSCR is embedded in the proposed LDO regulator, reliability cannot be guaranteed.…”

Compact MOS-triggered SCR with faster turn-on speed for ESD protection

“…To reduce the trigger voltage and enhance the turn-on efficiency of SCR, some advanced techniques such as gate-coupled technique [5], substrate-triggered technique [6], static triggered technique [7] and base-modulated technique [8] are employed. Recently, an initial-on PMOS-triggered SCR device is reported [9] and further optimizations on the MOS-triggered SCR devices for ESD protection are studied [10].…”

“…In this paper, based on the optimized merged MOS-triggered SCR structure in [10], a compact MOS-triggered SCR is proposed, which has a lower trigger voltage, a faster turn-on speed, a lower on-resistance, a lower clamped voltage and a higher failure current than the merged MOS-triggered SCR counterpart. The high turn-on efficiency, low clamping voltage and high failure current characteristics make this power clamp device more attractive in advanced CMOS process.…”

Field Effect Resistor, a single-device-at-pad solution for ESD protection in deeply scaled SOI technology

“…The pad-based local clamping scheme (Fig. 1b) [3] incorporating SCR-based devices with trigger mechanism [4][5][6] or resistive devices [7] reduces the pad voltage build-up by avoiding the power buses. However, similar to the railbased design, two ESD devices are required for current shunting in both directions (from I/O pad to power buses and vice versa).…”