Optimization of TSV Leakage in Via-Middle TSV Process for Wafer-Level Packaging

Abstract

Through silicon via (TSV) offers a promising solution for the vertical connection of chip I/O, which enables smaller and thinner package sizes and cost-effective products by using wafer-level packaging instead of a chip-level process. However, TSV leakage has become a critical concern in the BEOL process. In this paper, a Cu-fulfilled via-middle TSV with 100 µm depth embedded in 0.18 µm CMOS process for sensor application is presented, focusing on the analysis and optimization of TSV leakage. By using etch process, substrate defect, and thermal processing co-optimization, TSV leakage failure can be successfully avoided, which can be very instructive for the improvement in TSV wafer-level package yield as well as device performance in advanced semiconductor technology.

Effect of Ammonium Citrates as an Auxiliary Complexing Agent in TSV Copper Film CMP

“…Through Silicon Via (TSV) is a through hole in the z-axis direction on a silicon substrate, and the conductive material copper is filled in the through hole, thereby realizing the interconnection between different functional chips. 1,2 Compared with the previous technology, TSV can make the chips have the highest stacking density in the threedimensional direction, the shortest interconnection between chips, and the smallest external size, thereby greatly improving the signal transmission speed of the chip and reducing the power consumption. It is the most advanced electronic packaging technology.…”