Through silicon via (TSV) offers a promising solution for the vertical connection of chip I/O, which enables smaller and thinner package sizes and cost-effective products by using wafer-level packaging instead of a chip-level process. However, TSV leakage has become a critical concern in the BEOL process. In this paper, a Cu-fulfilled via-middle TSV with 100 µm depth embedded in 0.18 µm CMOS process for sensor application is presented, focusing on the analysis and optimization of TSV leakage. By using etch process, substrate defect, and thermal processing co-optimization, TSV leakage failure can be successfully avoided, which can be very instructive for the improvement in TSV wafer-level package yield as well as device performance in advanced semiconductor technology.
This work studied queue time between PVD and ECD in a 200mm TSV application. The proposed new PVD condition successfully extended queue time from the original 2-4 hours to at least two weeks. The original PVD condition was found to produce a Cu seed orientation of primarily (200) Cu. This produced a very rough post-plating surface when post-PVD queue time exceeded four hours. The orientation (200) appears to affect gap-fill capability when queue time exceeded four hours. With the new PVD condition, Cu seed orientation was optimized to be primarily (111) Cu, which created a shiny and clear post-plating surface. As a result, the vias could be filled well as long as two weeks after PVD. Copper seed recrystallization and post-plating morphology were found to be sensitive to nitrogen content in the barrier and to the bias power during Cu seed formation.
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