Optimization of the Store-and-Generate Based Built-in Self-Test

Abstract

Classical built-in self-test (BIST) architectures are usually relying on linear feedback shift registers (LFSR) for test set generation and test response compaction. This paper is based on extension of the classical BIST, namely hybrid BIST, where pseudorandom test patterns are complemented with precomputed deterministic test patterns to increase the fault coverage and reduce test time. We will propose a method, based on store-and-generate approach, to find the optimal balance between pseudorandom and stored deterministic test patterns. The objective is to minimize the test time at given memory constraints, without losing test quality. We propose an iterative search method and the experimental results on benchmark circuits have proved the efficiency of the proposed approach for hybrid BIST optimization.

Hybrid BIST Optimization Using Reseeding and Test Set Compaction

“…The main explanation lies in a fact that the proposed method handles the deterministic and pseudorandom sequences together and the test sets are optimized using a fast optimization method, based on cumulative fault coverage figures. The current implementation of the method [14] is not optimizing the length of the individual hybrid blocks and therefore also the result is worse than the result from [12].…”

“…The results are presented in Table 1, where we have depicted the test length of the final solution under different memory constraints (different amount of seeds. We have compared the method, proposed in this paper, with methods proposed in [12] and [14]. The method proposed in [12] was originally developed for multi-core systems but it can equally well be used also for individual cores.…”

“…We have not included here the CPU times, as with the proposed method we are calculating the entire solution space, while the methods from [12] and [14] can find a single solution for a predefined memory constraint. We are currently developing an optimization heuristic that would help us to avoid calculation of the complete curves and thereafter the comparison of CPU times is also possible.…”

“…One possible solution was proposed in [14], however, the results were far from optimal. In the following section we are going to propose a new method that is based on test set compaction for reducing the length of the reseeding blocks.…”

“…Therefore, it might happen that the test sequences could substantially be shortened if the tests are applied in different order or the sequences are split into smaller sequences and applied in a mixed mode. Such a mixed mode approach is commonly known as reseeding and in our recent work we successfully combined the hybrid BIST optimization techniques with reseeding ideas [14]. However, the previously proposed approach does not take into account possibility to reduce the length of the hybrid test sequence by using test set compaction.…”