Hybrid BIST Optimization Using Reseeding and Test Set Compaction

Jervan, Gert; Orasson,; Kruus, Margus; Ubar, Raimund

doi:10.1109/dsd.2007.4341529

Cited by 4 publications

(3 citation statements)

References 12 publications

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“…RPR faults [25] are faults that are not detectable by PRPG test patterns due their linear dependency and auto-correlation. The main alternatives to address RPR faults are the insertion of extra test points [15] [16] or the use of deterministic information stored outside chip [17]. As storing some information outside chip seems to make the LBIST less Built-in and depending of amount of required data this can become a problem.…”

Section: Logic Built-in Self-testmentioning

confidence: 99%

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A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns

Alves

Barros

2009

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes

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The claim for new functionalities regarding the improvement of dependability of electronic systems and also the need for managing the time spent during test make the Built-in-Self-Test mechanism (BIST) a promising feature to be integrated in current IC flows. There are a lot of types of BIST: Memories BIST, Logical BIST (LBIST) and also some mechanisms used to test analog parts of circuit. Traditional LBIST uses on-chip hardware to generate all test patterns with a pseudo-randompattern-generator (PRPG) and analyze the output signature generated by a multiple-input-signature-register (MISR). This approach requires the insertion of extra test-points or storing information outside chip to enable achieving a test coverage >98%. Also generating all test stimuli implies in a sacrifice of test application time, which can be acceptable for some small systems to perform self-test during boot up but could become a negative aspect when testing System-on-chip (SOC) ICs. The current IC development flow insert scan chains and generates automatically scan tests patterns to achieve high fault coverage for manufacturing test. Scan data compression techniques have proven to be very useful for reducing test cost while reducing test data volume and test application time. This work proposes the reuse of compressed scan test patterns used during manufacturing test to implement a LBIST with the goal of testing the circuit when it is already in field. The proposed LBIST mechanism aims to uncover defects that could occur due to the wear out of the circuit. A scan test pattern based LBIST architecture and a semi-automatic development flow are proposed and validated in a real word SoC testcase.

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Section: Logic Built-in Self-testmentioning

confidence: 99%

“…There a class of works that uses hybrid LBIST [8], [12], [17], [19], [21] [3] proposed an architecture that reduces external test data stored in tester memory, reduces the number of pseudorandom patterns and can be applied using STUMPS architecture with a minor modification.…”

Section: Chapter 3 -Related Workmentioning

confidence: 99%

A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns

Alves

Barros

2009

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes

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“…Many works have been done for improving LFSR based BIST architectures [12][13][14], LFSR reconfiguration [15], and optimized reseeding [16][17][18] to get high fault coverage and less test application time. In order to achieve high fault coverage alongside with low test application time, some works [8][9][10][11] have attempted to use hybrid BIST methods that include scan based approaches. The work in [19] has proposed a hybrid BIST method which makes use of both internally generated pseudo random test data and test data from external sources.…”

Section: Introductionmentioning

confidence: 99%

BILBO-friendly hybrid BIST architecture with asymmetric polynomial reseeding

Sadredini

Najafi

Navabi

2012

The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012)

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Abstract-By advances in technology, integrated circuits have come to include more functionality and more complexity in a single chip. Although methods of testing have improved, but the increase in complexity of circuits, keeps testing a challenging problem. Two important challenges in testing of digital circuits are test time and accessing the circuit under test (CUT) for testing. These challenges become even more important in complex system on chip (SoC) zone. This paper presents a multistage test strategy to be implemented on a BIST architecture for reducing test time of a simple core as solution for more global application of SoC testing strategy. This strategy implements its test pattern generation and output response analyzer in a BILBO architecture. The proposed method benefits from an irregular polynomial BILBO (IP-BILBO) structure to improve its test results. Experimental results on ISCAS-89 benchmark circuits show an average of 35% improvement in test time in proportion to pervious work.

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A multi-output technique for high fault coverage in test-per-scan BIST

Abu-Issa

Quigley

2008

2008 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era

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Hybrid BIST Optimization Using Reseeding and Test Set Compaction

Cited by 4 publications

References 12 publications

A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns

A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns

BILBO-friendly hybrid BIST architecture with asymmetric polynomial reseeding

A multi-output technique for high fault coverage in test-per-scan BIST

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