Optimization of Microring-Based Interconnection by Leveraging the Asymmetric Behaviors of Switching Elements

Yuen, P. H.; Chen, Lian-Kuan

doi:10.1109/jlt.2013.2253761

Cited by 14 publications

(8 citation statements)

References 17 publications

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“…The proposed HCROS architecture was optimized and a certain number of OSEs were reduced [25]. By reducing the number of OSEs we can achieve a more compact footprint for the optical switch and a reduction in OSEs also minimizes the power consumption and IL caused due to the drop/bar state of OSEs, which consume more power in the drop/bar state than the through/cross state [38]. However, this reduction in OSEs count can lead to a decrease in some routing choices that can deteriorate the performance for some applications.…”

Section: Optimized 6-port Non-blocking Reconfigurable Optical Switch mentioning

confidence: 99%

“…In this article, we assumed that the IL and power consumption of 2 × 2 MR based OSE are as per the specifications listed in Table 8. The values shown are the result of experimental measurements and incorporate the effect of process variations caused by physical parameters [38]. In the rest of this article, our results and analysis rely on the specifications provided in Table 8.…”

Section: Calculation Of Insertion Loss and Power Consumption For Hcrosmentioning

confidence: 99%

“…MR is widely used as a basic component in optical interconnects due to its compact size and compatibility with CMOS. The functionality of 2 × 2 MR based OSE is illustrated in Figure 1a,b, where 2 × 2 OSE consists of two crossing waveguides and two MRs [19], [38]. When the resonant frequency of MR is not the same as the modulated signal, the optical signal simply passes through the waveguide intersection.…”

Section: Introductionmentioning

confidence: 99%

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HoneyComb ROS: A 6 × 6 Non-Blocking Optical Switch with Optimized Reconfiguration for ONoCs

Yahya

Gao

et al. 2019

Electronics

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Silicon photonics has become a commonly used paradigm for on-chip interconnects to meet the requirements of higher bandwidth in computationally intensive applications for manycore processors. Design of an optical switch is a vital aspect while constructing an optical NoC topology which influences the performance of network. We present a HoneyComb optimized reconfigurable optical switch (HCROS), a 6 × 6 non-blocking optical switch where optimized reconfiguration of optical links utilizing the states of basic 2 × 2 optical switching elements (OSE) was achieved while keeping the input-output (I/O) interconnection intact. The proposed 6-port HCROS architecture was further optimized to reduce the number of OSEs to minimize overall power consumption. We proposed a generic algorithm to find the optimal switching combination of OSEs for a particular I/O link to minimize the insertion loss and power consumption. In comparison to other non-blocking architectures, a maximum of 66% reduction in OSEs was observed for the optimized HCROS, which consumes only 12 OSEs. Simulations were performed for all 720 I/O links in different configurations to evaluate the power consumption and insertion loss. We observed up to 92% power savings in the case of optimized HCROS as compared to un-optimized HCROS, and a 79% minimization in insertion loss was also reported as a result of optimization.

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Section: Optimized 6-port Non-blocking Reconfigurable Optical Switch mentioning

confidence: 99%

Section: Calculation Of Insertion Loss and Power Consumption For Hcrosmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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HoneyComb ROS: A 6 × 6 Non-Blocking Optical Switch with Optimized Reconfiguration for ONoCs

Yahya

Gao

et al. 2019

Electronics

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“…Design of an optical switch based on aforementioned non-blocking architectures, with minimal number of switching units, needs optimization of OSUs. Several schemes are adopted to construct optical switch with optimal number of switching units and different methods are proposed to optimize the number of OSUs [14]- [20].…”

Section: Introductionmentioning

confidence: 99%

“…A mathematical theorem is presented in [19] to find the routing path in MR based Benes network which can reduce power consumption of switch network. Another approach to minimize computational time for optimal optical switch network using heuristics is proposed in [20]. However, optimization of optical switch along with scalability to meet future requirements of ONoCs requires a comprehensive framework which is lacking in previously proposed methodologies.…”

Section: Introductionmentioning

confidence: 99%

An Algorithmic Framework to Construct Optical Switch via Scaling From N-to-2N Ports for Optical Network on Chip

Yahya

Gao

et al. 2019

IEEE Access

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Optical network-on-chip (ONoC), designed with non-blocking optical switches, is gaining a significant research attention to meet the upcoming requirements of higher throughput, larger bandwidth, lower latency, and reduced power consumption for manycore processors. In this paper, we propose an algorithmic framework to construct non-blocking optical switches with multiple interconnection possibilities. The design is accomplished by scaling the optical switch from N-to-2N ports using two intermediate mapping matrices each of size 2N × 2N. These mapping matrices are the row and column permutations of identity matrices, where 1's represent passive interconnections among the optical switching units (OSUs). The proposed framework provides validation to the design by identifying all the non-blocking permutations of the mapping matrices, thereby, providing a flexibility to adopt any permutation as an interconnection scheme. Furthermore, it has the ability to quantify the redundancy in switching combinations which exists for any input-to-output routing, authenticates the non-blocking feature of the optical switch and to reduce the number of optical switching units while preserving the non-blocking characteristic. For the scaled 4 × 4 and 6 × 6 optical switches, we respectively identified 16 and 192 different interconnections to build multiple non-blocking switches. Moreover, a 20% reduction in OSUs is achieved by optimizing a 6 × 6 switch. The influence of the insertion loss, power consumption, and crosstalk noise on various scaled optical switch networks are also analyzed and compared with several existing optical switch topologies. INDEX TERMS Optical network-on-chip (ONoC), optical switch, optimization, scalability, silicon nanophotonics. The associate editor coordinating the review of this manuscript and approving it for publication was Sukhdev Roy. network increases, OSU count also increases which leads to higher latency, poor power consumption and insertion loss [5]. Scalability of high radix optical switch, designed for high performance applications, requires special design considerations to alleviate the intrinsic characteristics of insertion loss, crosstalk noise and power consumption in optical onchip interconnects. Increase in switching units also affects the complexity and footprint of optical switch [6]. Optimal number of OSUs and their configuration can reduce overall crosstalk noise, insertion loss and power consumption for the optical switch [7]. Several non-blocking architectures based on different network topologies have been proposed in literature

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Non-blocking 2 × 2 switching unit based on nested silicon microring resonators with high extinction ratios and low crosstalks

Jiang

Pan

et al. 2014

Chin. Sci. Bull.

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Optimization of Microring-Based Interconnection by Leveraging the Asymmetric Behaviors of Switching Elements

Cited by 14 publications

References 17 publications

HoneyComb ROS: A 6 × 6 Non-Blocking Optical Switch with Optimized Reconfiguration for ONoCs

HoneyComb ROS: A 6 × 6 Non-Blocking Optical Switch with Optimized Reconfiguration for ONoCs

An Algorithmic Framework to Construct Optical Switch via Scaling From N-to-2N Ports for Optical Network on Chip

Non-blocking 2 × 2 switching unit based on nested silicon microring resonators with high extinction ratios and low crosstalks

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