An Algorithmic Framework to Construct Optical Switch via Scaling From N-to-2N Ports for Optical Network on Chip

Abstract

Optical network-on-chip (ONoC), designed with non-blocking optical switches, is gaining a significant research attention to meet the upcoming requirements of higher throughput, larger bandwidth, lower latency, and reduced power consumption for manycore processors. In this paper, we propose an algorithmic framework to construct non-blocking optical switches with multiple interconnection possibilities. The design is accomplished by scaling the optical switch from N-to-2N ports using two intermediate mapping matrices each of size 2N × 2N. These mapping matrices are the row and column permutations of identity matrices, where 1's represent passive interconnections among the optical switching units (OSUs). The proposed framework provides validation to the design by identifying all the non-blocking permutations of the mapping matrices, thereby, providing a flexibility to adopt any permutation as an interconnection scheme. Furthermore, it has the ability to quantify the redundancy in switching combinations which exists for any input-to-output routing, authenticates the non-blocking feature of the optical switch and to reduce the number of optical switching units while preserving the non-blocking characteristic. For the scaled 4 × 4 and 6 × 6 optical switches, we respectively identified 16 and 192 different interconnections to build multiple non-blocking switches. Moreover, a 20% reduction in OSUs is achieved by optimizing a 6 × 6 switch. The influence of the insertion loss, power consumption, and crosstalk noise on various scaled optical switch networks are also analyzed and compared with several existing optical switch topologies. INDEX TERMS Optical network-on-chip (ONoC), optical switch, optimization, scalability, silicon nanophotonics. The associate editor coordinating the review of this manuscript and approving it for publication was Sukhdev Roy. network increases, OSU count also increases which leads to higher latency, poor power consumption and insertion loss [5]. Scalability of high radix optical switch, designed for high performance applications, requires special design considerations to alleviate the intrinsic characteristics of insertion loss, crosstalk noise and power consumption in optical onchip interconnects. Increase in switching units also affects the complexity and footprint of optical switch [6]. Optimal number of OSUs and their configuration can reduce overall crosstalk noise, insertion loss and power consumption for the optical switch [7]. Several non-blocking architectures based on different network topologies have been proposed in literature

Network Security Analysis Using Switch Port Security CPT

“…Network security is a system that prevents unwanted activities by identifying users who do not have network access rights [12]. Connecting your computer to other computers through wired or wireless networks allows others to access data, modify content, and even delete data online [13]. Vulnerabilities exist everywhere, from devices and data pathways to applications and users.…”