Optimization of low voltage n-channel LDMOS devices to achieve required electrical and lifetime SOA

Pendharkar, S.; Higgins, R.; Debolske, T.; Efland, T.; Nehrer, B.

doi:10.1109/ispsd.2002.1016221

Cited by 9 publications

(4 citation statements)

References 4 publications

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“…This is achieved by the localoxidation-of-silicon (LOCOS) technology, although it decreases the device density. Furthermore, hot-carrier trapping in these devices leads to an undesirable shift in electrical characteristics [28], [29]. In more recent technologies, STI has been used to create a thick-oxide Fig.…”

Section: ) Shallow Trench Isolation (Sti) Demosmentioning

confidence: 99%

Part I: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices

Shrivastava

Baghini

Gossner

et al. 2010

IEEE Trans. Electron Devices

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Abstract-In this paper, the optimization issues of various drain-extended devices are discussed for input/output applications. The mixed-signal performance, impact of process variations, and gate oxide reliability of these devices are compared. Lightly doped drain MOS (LDDMOS) was found to have a moderate performance advantage as compared to shallow trench isolation (STI) and non-STI drain-extended MOS (DeMOS) devices. Non-STI DeMOS devices have improved circuit performance but suffer from the worst gate oxide reliability. Incorporating an STI region underneath the gate-drain overlap improves the gate oxide reliability, although it degrades the mixed-signal characteristics of the device. The single-halo nature of DeMOS devices has been shown to be effective in suppressing the short-channel effects.Index Terms-Drain-extended MOS (DeMOS), hot carrier, input/output, lightly doped drain MOS (LDDMOS), mixed signal, reduced surface field (RESURF), reliability.

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Section: ) Shallow Trench Isolation (Sti) Demosmentioning

confidence: 99%

Part I: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices

Shrivastava

Baghini

Gossner

et al. 2010

IEEE Trans. Electron Devices

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“…1b). Carriers heat up in this field and induce weak avalanche and HCI injection into the dielectric (typically near the gate) [5]. Electric field in devices using extensions and featuring the RESURF effect [6], can be shaped such that the electric field peaks both at the gate edge and at the extension-drain junction (double peak).…”

Section: Optimization Of Field Distributionmentioning

confidence: 99%

HCI reliability control in HV-PMOS transistors: Conventional EDMOS vs. Dielectric RESURF and lateral field plates

Perez‐González

Šonský

Heringa

et al. 2009

2009 21st International Symposium on Power Semiconductor Devices &Amp; IC's

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“…6, those LDMOST devices with a longer L OV have a lower maximum I SUB value, but have a shorter hot-carrier device lifetime. However, this can be explained by the hot-carrier injection efficiency.…”

mentioning

confidence: 95%

“…[3][4][5] Up to now, most of the studies designed to optimize the drain junction have focused on adjusting the doping concentration and improving the structure. More recently, 6) two-dimensional modeling is used to analyze the hot carrier degradation dependence on the gate-to-drift overlap length (L OV ), but does not show the optimized L OV .…”

Section: Introductionmentioning

confidence: 99%

Optimizing the Gate-to-Drift Overlap Length of Lateral Double Diffused Metal–Oxide–Semiconductor Field Effect Transistor Devices to Improve Hot-Carrier Device Lifetime

Na¹,

Ha²,

Choi³

et al. 2006

jjap

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In this study, the gate-to-drift overlap length of lateral double diffused metal–oxide–semiconductor field effect transistor (LDMOST) devices is optimized in order to increase their hot-carrier lifetime. LDMOST devices with drift regions are fabricated using a 0.25 µm complementary metal–oxide–semiconductor (CMOS) process. The gate-to-drift overlap lengths in the drift region are 0.1, 0.4, 0.8, and 1.1 µm, respectively. The breakdown voltages, on-resistances and hot-carrier degradations of the fabricated LDMOST devices are characterized. The LDMOST device with a gate-to-drift overlap length of 0.4 µm showed the longest on-resistance hot-carrier lifetime of 9.34 ×105 s, along with a breakdown voltage of 22 V and an on-resistance of 23 mΩ·mm2.

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Optimization of low voltage n-channel LDMOS devices to achieve required electrical and lifetime SOA

Cited by 9 publications

References 4 publications

Part I: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices

Part I: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices

HCI reliability control in HV-PMOS transistors: Conventional EDMOS vs. Dielectric RESURF and lateral field plates

Optimizing the Gate-to-Drift Overlap Length of Lateral Double Diffused Metal–Oxide–Semiconductor Field Effect Transistor Devices to Improve Hot-Carrier Device Lifetime

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