HCI reliability control in HV-PMOS transistors: Conventional EDMOS vs. Dielectric RESURF and lateral field plates

Perez‐González, José; Šonský, Jan; Heringa, A.; Benson, J. D.; Chiang, Po-Jui; Yao, Chengcheng; Sua, R.Y.

doi:10.1109/ispsd.2009.5158001

Cited by 7 publications

(3 citation statements)

References 6 publications

(4 reference statements)

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“…The HVI needs to be extended across the entire drift region because the integrated HV device always has a closed structure with HV at the inner drain. The HVI line may cause a significant reduction in V B because of the strong field modulation effect [39,40] , which may also induce hot carrier injection in power devices [41] . The physical essence of HVI may be equivalent to the introduction of positive charges Q E on the surface of a device and under the HVI line and V I is the potential difference between the upper and lower interfaces of the insulator.…”

Section: Hvi Technologymentioning

confidence: 99%

Review of technologies for high-voltage integrated circuits

Zhang

Zhu

et al. 2022

Tsinghua Sci. Technol.

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High-Voltage power Integrated Circuits (HVICs) are widely used to realize high-efficiency power conversions (e.g., AC/DC conversion), gate drivers for power devices and LED lighting, and so on. The Bipolar-CMOS-DMOS (BCD) process is proposed to fabricate devices with bipolar, CMOS, and DMOS modes, and thereby realize the single-chip integration of HVICs. The basic integrated technologies of HVICs include High-Voltage (HV) integrated device technology, HV interconnection technology, and isolation technology. The HV integrated device is the core of HVICs. The basic requirements of the HV integrated device are high breakdown voltage, low specific on-resistance, and process compatibility with low-voltage circuits. The REduced SURFace field (RESURF) technology and junction termination technology are developed to optimize the surface field of integration power devices and breakdown voltage. Furthermore, the ENhanced DIelectric layer Field (ENDIF) and REduced BULk Field (REBULF) technologies are proposed to optimize bulk fields. The double/triple RESURF technologies are further developed, and the superjunction concept is introduced to integrated power devices and to reduce the specific on-resistance. This work presents a comprehensive review of these technologies, including the innovation technologies of the authors' group, such as ENDIF and REBULF, substrate termination technology prospective integrated technologies and HVICs in wide band gap semiconductor materials are also discussed.

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Section: Hvi Technologymentioning

confidence: 99%

Review of technologies for high-voltage integrated circuits

Zhang

Zhu

et al. 2022

Tsinghua Sci. Technol.

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“…The poly-silicon length will affect the electric field of oxide and interface. According to the RESURF principles [12][13][14][15], the interface electric field eventually defines the reliability of an HV device.…”

Section: Hv Nldmos Devicementioning

confidence: 99%

Influence of a Deep NBL Structure on ESD/Latch-Up Immunities in the Power Device nLDMOS

Chen

2013

AMR

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In this paper, we propose a novel high-voltage (HV) nLDMOS transistor with a small Ron resistance, low trigger voltage (Vt1) and high holding voltage (Vh) characteristics. Here, we introduce a deep N+-buried-layer (NBL) into this HV nLDMOS to evaluate the ESD/latch-up (LU) parameters variation. These electric snapback parameters affect the reliability of proposed device and its performance. Eventually, we expect this proposed HV stucture processed better characteristic behaviors, which can be applied to the power electronics and ESD protection application of HV ICs.

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“…[3][4][5][6][7] An HV nLDMOS is usually used as the level-up shifter to transfer digital signals from the ground to the floating source of a HS power switch. [8][9][10] At the early stages of technology development of an HVIC, [11][12][13] the conventional design comprises a high voltage junction termination (HVJT) with a large drift region and a level shifter, which is placed outside the HVJT structure. The drain electrode of a level shifter is connected to the HS region via a high voltage interconnection (HVI), which must be routed over an area of HVJT structure, to transfer the signal from LS region to HS region.…”

Section: Introductionmentioning

confidence: 99%

Improving breakdown voltage for 120 V level up shifter by using vertical and lateral assisted depletion layers in 0.35 μm CMOS technology

Ningaraju¹,

Lin²,

Chen³

et al. 2020

Jpn. J. Appl. Phys.

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A novel isolation structure featuring a vertical assisted depletion layer (VADL) by p-buried layer (PBL) and lateral assisted depletion layer (LADL) by micro-n-well (μNW) for 120 V level up shifter is proposed. VADL and LADL efficiently prevents the premature breakdown of level shifter by fully depleting nLDMOS drain region and p-isolation (P-ISO) region respectively. By the effect of the electric field modulation, more uniform lateral and vertical electric fields are obtained due to the insertion of the VADL and LADL, which improves the breakdown voltage (BV) and device reliability. The breakdown and reliability mechanisms are investigated in detail by theoretical analysis, TCAD simulations and experimental measurements. The measured results shows, BV of 160 V and almost no HTRB degradation is seen after 168 h of stress. In addition, the new structure is fully compatible with standard 0.35 μm CMOS technology. Hence, it is not only a performance booster but also a low-cost solution.

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HCI reliability control in HV-PMOS transistors: Conventional EDMOS vs. Dielectric RESURF and lateral field plates

Cited by 7 publications

References 6 publications

Review of technologies for high-voltage integrated circuits

Review of technologies for high-voltage integrated circuits

Influence of a Deep NBL Structure on ESD/Latch-Up Immunities in the Power Device nLDMOS

Improving breakdown voltage for 120 V level up shifter by using vertical and lateral assisted depletion layers in 0.35 μm CMOS technology

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