2021 IEEE Applied Power Electronics Conference and Exposition (APEC) 2021
DOI: 10.1109/apec42165.2021.9487102
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Optimization of Electric-Field Grading Plates in a PCB-Integrated Bus Bar for a High-Density 10 kV SiC MOSFET Power Module

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Cited by 5 publications
(4 citation statements)
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“…These geometrical singularities, largely studied in the literature [5], induce a clear voltage withstand issuei.e., presence of partial discharges (PDs) and possible breakdown voltage (BDV)-that needs to be considered during the electrical design phase. The literature presents several techniques to manage the electric field reinforcement at the triple point [6]. For instance, Waltrich et al [7] propose applying a dielectric coating to reduce the electric field at this location.…”
Section: Introductionmentioning
confidence: 99%
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“…These geometrical singularities, largely studied in the literature [5], induce a clear voltage withstand issuei.e., presence of partial discharges (PDs) and possible breakdown voltage (BDV)-that needs to be considered during the electrical design phase. The literature presents several techniques to manage the electric field reinforcement at the triple point [6]. For instance, Waltrich et al [7] propose applying a dielectric coating to reduce the electric field at this location.…”
Section: Introductionmentioning
confidence: 99%
“…A solution developed in [10,11] for high-voltage DC-link busbars lies in modifying the electric field configuration thanks to a capacitive field grading inside the PCB structure, with the advantage of a classical PCB manufacturing process. With this technique, the electric field reinforcement originally located at the triple point is reduced and transferred to another material with better dielectric rigidity than air, i.e., FR4 resin.…”
Section: Introductionmentioning
confidence: 99%
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