Optimization of a fully integrated low power CMOS GPS receiver

Abstract

This paper describes an optimization technique able to optimize a complete wireless receiver architecture in a reasonable amount of time. The optimizer alternates between spice level optimizations of simple building blocks and a full architecture optimization of the whole based on accurate models of the building blocks. The models of the building blocks are interpolated over the data points acquired in the Spice level simulations. The optimizer technique has been applied to the optimization of an architecture for a GPS receiver. The optimal design has been implemented in a standard 0.25µm CMOS process.

Phase-locked loop synthesis using hierarchical divide-and-conquer multi-optimization

“…The variable space includes loop component values and charge-pump current while the objective space consists of phase margin, jitter peaking, settling behavior, and noise introduced by the resistor of the LPF. All optimization objectives are derived from the PLL closed-loop transfer function (2) and are shown in (3) through (6) [7].…”

“…1, a typical PLL consists of a phase/frequency detector (PFD), a charge pump (CP), a loop filter (LPF), a voltagecontrolled oscillator (VCO), a divide-by-2 prescaler, and a frequency divider. Because of its size and the fact that in most cases it works with both high and low frequency signals, transistor level simulation time is lengthy and optimization of the entire system is nearly impossible [2]- [3].…”