Optimization Methods for Post-Bond Testing of 3D Stacked ICs

Noia, Brandon; Chakrabarty, Krishnendu; Marinissen, Erik Jan

doi:10.1007/s10836-011-5233-8

Cited by 26 publications

(16 citation statements)

References 21 publications

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“…A DfT architectural optimization for 3D-SIC is proposed in [Noia12] to minimize the test application time for mid-or post-bond testing. Optimal architecture and the corresponding test schedule are obtained for a scenario where only the post-bond testing is performed.…”

Section: Related Work 29mentioning

confidence: 99%

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Thermal Issues in Testing of Advanced Systems on Chip

Ghaleshahi¹

2015

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Many cutting-edge computer and electronic products are powered by advanced Systems-on-Chip (SoC). Advanced SoCs encompass superb performance together with large number of functions. This is achieved by efficient integration of huge number of transistors. Such very large scale integration is enabled by a core-based design paradigm as well as deepsubmicron and 3D-stacked-IC technologies. These technologies are susceptible to reliability and testing complications caused by thermal issues. Three crucial thermal issues related to temperature variations, temperature gradients, and temperature cycling are addressed in this thesis.Existing test scheduling techniques rely on temperature simulations to generate schedules that meet thermal constraints such as overheating prevention. The difference between the simulated temperatures and the actual temperatures is called temperature error. This error, for past technologies, is negligible. However, advanced SoCs experience large errors due to large process variations. Such large errors have costly consequences, such as overheating, and must be taken care of. This thesis presents an adaptive approach to generate test schedules that handle such temperature errors.Advanced SoCs manufactured as 3D-stacked-ICs experience large temperature gradients. Temperature gradients accelerate certain early-life defect mechanisms. These mechanisms can be accelerated using gradientbased, burn-in like operations so that the defects are detected before shipping. Moreover, temperature gradients exacerbate some delay-related defects. In order to detect such defects, testing must be performed when appropriate temperature-gradients are enforced. Schedule-based techniques that enforces the temperature-gradients for burn-in like operations and delay testing are proposed in this thesis. Abstract iiThe last thermal issue addressed by this thesis is related to temperature cycling. Temperature cycling test procedures are usually applied to safetycritical systems to detect cycling-related early-life failures. Such failures affect advanced SoCs, particularly through-silicon-via structures in 3D-stacked-ICs. An efficient schedule-based cycling-test technique that combines cycling acceleration with testing is proposed in this thesis. The proposed technique fits into existing 3D testing procedures and does not require temperature chambers. Therefore, the overall cycling acceleration and testing cost can be drastically reduced.All the proposed techniques have been implemented and evaluated with extensive experiments based on ITC'02 benchmarks as well as a number of 3D stacked ICs. Experiments show that the proposed techniques work effectively and reduce the test costs. We have also developed a fast temperature simulation technique based on a closed-form solution for the temperature equations. Experiments demonstrate that the proposed simulation technique reduces the test schedule generation time by more than half.iii Populärvetenskaplig sammanfattningMånga banbrytande dator-och elektronikprodukter drivs...

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Section: Related Work 29mentioning

confidence: 99%

“…Optimal architecture and the corresponding test schedule are obtained for a scenario where only the post-bond testing is performed. It is demonstrated that the optimal architecture and schedule are different for the scenario where a mid-bond testing is added to the existing post-bond tests [Noia12].…”

Section: Related Work 29mentioning

confidence: 99%

Thermal Issues in Testing of Advanced Systems on Chip

Ghaleshahi¹

2015

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“…Several papers exist that deal with 3D-DfT and its optimization [2][3][4][5][6][7][8]. This paper is based on the 3D-DfT architecture originally proposed for logic-on-logic stacks by Marinissen et al in [9][10][11][12].…”

Section: Prior Work On 3d-dftmentioning

confidence: 99%

Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers

Papameletis

Keller

Chickermane

et al. 2013

2013 18th Ieee European Test Symposium (Ets)

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Three-dimensional stacked integrated circuits (3D-SICs) implemented with through-silicon vias (TSVs) and micro-bumps open new horizons for faster, smaller, and more energy-efficient chips. As all micro-electronic structures, these 3D chips and their interconnects need to be tested for manufacturing defects. Previously, we defined, implemented, and automated a 3D-DfT (Design-for-Test) architecture that provides modular test access for 3D-SICs containing monolithic logic dies in a single-tower stack. However, the logic dies comprising a 3D-SIC typically are complex System-on-Chip (SoC) designs that include embedded intellectual property (IP) cores, wrapped for modular test. Also, multi-tower 3D-SICs have started to emerge. In this paper, our existing 3D-DfT architecture is extended with support for wrapped embedded IP cores and multi-tower stacks and its implementation is automated with industrial electronic design automation (EDA) tools.

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“…b) Soft dies: test architecture for each die is not predefined; it may be structured during architecture design. In this case, scan chains for each test module are given, but test wrappers for each module and TAM are designed during 3-D TAM design [6]. So, these dies are most flexible.…”

Section: Fig 1 Simple Example Of 3d Sicmentioning

confidence: 99%

“…Some works [4], [5] and [6], have been presented on testing of different type 3D SICs. In [4], problems had introduced with test architecture optimization for both hard and soft dies.…”

Section: Fig 1 Simple Example Of 3d Sicmentioning

confidence: 99%

Post-bond Stack Testing for 3D Stacked IC

Roy

Giri

et al. 2012

Progress in VLSI Design and Test

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Abstract. In the embedded system design Through-silicon-via (TSV) based 3D stacked ICs (SICs) play an important role in semiconductor industry. But testing of these SICs are required during 3D assembly because different die stacking steps may introduce defects. In this paper, we address test architecture optimization for 3D stacked ICs implemented with hard die means where dielevel test architecture is fixed. We consider two different SIC configurations and derive optimal solution to minimize overall test time when complete stack and multiple partial stacks, need to be tested. Results are performed for two handcrafted 3D SICs comprising of various SoCs from ITC'02 SoC test benchmarks. In this work we consider the test architecture optimization for 3D SIC where each die consists of one SoC. We present test schedules and corresponding test lengths for every multiple insertions and also show that total test lengths are decreased with the increasing number of test pins.

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Optimization Methods for Post-Bond Testing of 3D Stacked ICs

Cited by 26 publications

References 21 publications

Thermal Issues in Testing of Advanced Systems on Chip

Thermal Issues in Testing of Advanced Systems on Chip

Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers

Post-bond Stack Testing for 3D Stacked IC

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