Optimising the SHA‐512 cryptographic hash function on FPGAs

Abstract

In this study, novel pipelined architectures, optimised in terms of throughput and throughput/area factors, for the SHA-512 cryptographic hash function, are proposed. To achieve this, algorithmic-and circuit-level optimisation techniques such as loop unrolling, re-timing, temporal pre-computation, resource re-ordering and pipeline are applied. All the techniques, except pipeline are applied in the function's transformation round. The pipeline was applied through the development of all the alternative pipelined architectures and implementation in several Xilinx FPGA families and they are evaluated in terms of frequency, area, throughput and throughput/area factors. Compared to the initial un-optimised implementation of SHA-512 function, the introduced five-stage pipelined architecture improves the both the throughput and throughput/area factors by 123 and 61.5%, respectively. Furthermore, the proposed five-stage pipelined architecture outperforms the existing ones both in throughput (3.4× up to 16.9×) and throughput/area (19.5% up to 6.9×) factors.

Acceleration of the Secure Hash Algorithm-256 (SHA-256) on an FPGA-CPU Cluster Using OpenCL

“…Several optimizations of SHA-256 were recently published works. Some focused on optimizing SHA-256 hardware accelerator implementations for FPGA or ASIC by adopting pipelined architectures [16][17][18], while others adopted circuitlevel optimizations that shorten the critical path [19] or that reorder resource usage [20]. These works used a hardware description language (HDL) to implement the SHA-256 core and package it as an IP core [21].…”

SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey

“…A folded implementation of the Expander, employing only one adder, is proposed instead in [78], [79]. The unrolled implementation of the Expander is presented in [91], [95]. In [93], an architectural optimisation of the Expander is proposed, based on the delay balancing technique.…”

“…The approach is further improved in [97], most notably by adding recursion, obtaining an even improved hash core. The latter version is evaluated against different FPGA platforms in [91], where the corresponding architecture of the Expander is also described. Finally, [105] presents a multi-mode hash accelerator based on the same techniques.…”

An optimum security enabled System‐on‐Chip selection for Internet of Things applications using genetic algorithm modeling

“…The lightweight MX encryption algorithm was proposed aiming to produce high performance and suitable for copyright protection system and consumer electronics applications 8 . George et al has proposed the area optimized five‐stage pipelined secure hash algorithm (SHA) architecture that improves the area factor of about 9 . David et al demonstrated the two‐fish algorithm (TFA) that operates with clock frequency of 315 MHz to achieve the throughput of 48 GBPS 10 .…”