Optimal spare utilization for reliability and mean lifetime improvement of logic built-in self-repair

Koal, Tobias; Vierhaus, Heinrich Theodor

doi:10.1109/ddecs.2011.5783083

Cited by 11 publications

(2 citation statements)

References 14 publications

(18 reference statements)

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“…This is the main reason why only ad hoc methods exist in this area and the BISR architecture was introduced only for specific cores [5]- [7] and not as a generic architecture. Research was conducted to estimate the reliability of BISR architectures (considered again in the context of superscalar processors) [8]. The published estimation is based on the chip area occupied by BBs and switching elements (ratio to the chip area without backup is computed).…”

Section: Related Workmentioning

confidence: 99%

Generic built-in self-repair architectures for SoC logic cores

Baláž

Kristofik

Fischerova

2014

17th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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The built-in self-repair (BISR) concept is utilized and proven by industry mainly in regular structures of systemon-chips (SoCs) memory cores. On the other hand, the idea of self repair concept for logic cores introduced and developed in several papers is relatively new, as the irregular structure of these types of cores represents a serious limitation. However, there is a need of a complex BISR architecture that can be widely used on different types of logic cores in order to support further the reliability of SoCs. This paper presents a generic BISR architecture based on reconfigurable logic blocks (RLBs) applicable for any logic core inside a SoC together with in detail defined basic requirements guiding the architecture development and also algorithms handling fault detection and localization procedure.

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Section: Related Workmentioning

confidence: 99%

Generic built-in self-repair architectures for SoC logic cores

Baláž

Kristofik

Fischerova

2014

17th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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“…One approach has been to use reconfigurable modules in FPGAs, such as logic blocks or routing resources, to replace the defective modules [15]. Another approach is to use spare functional units on FPGAs [16], such as spare ALUs [17]. These approaches implement both the original and spare modules on a single FPGA.…”

Section: A Related Workmentioning

confidence: 99%

Repairing a 3-D Die-Stack Using Available Programmable Logic

Nepal

Alhelaly

Dworak

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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3D die-stacks hold great promise for increasing system performance, but difficulties in testing dies and assembling a 3D stack are leading to yield issues and slowing the large scale manufacturing of these devices. In many cases, a single defective die will kill the entire stack. To help mitigate this issue, we explore the possibility of repairing a stack that contains a defective die by utilizing an FPGA that has already been included in the stack for other purposes, such as performance enhancement. Specifically, we propose bypassing the defective portion of a non-programmable die by replacing the defective functionality with functionality on the FPGA. In this article, we discuss what additional logic must be added to an ASIC die to allow such a bypass to occur. We then show through detailed simulation of a 2.5D Xilinx FPGA how bypassing of logic can be achieved and throughput maintained even when the two different dies involved operate at different frequencies.Finally, we explore the performance of this technique in a superscalar, out-of-order processor, where different functional units are marked for replacement. Our simulation results show that not only can we salvage a device that would otherwise have to be discarded, but creating multiple copies of the defective partition in the FPGA can allow us to regain performance even when the latency of the units in the FPGA is longer than that of the original defective copy.

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