Optimal Design of Monolithic Integrated DC-DC Converters

Schrom, G.; Hazucha, P.; Paillet, F.; Gardner, Donald S.; Moon, Sung Tae; Karnik, Tanay

doi:10.1109/icicdt.2006.220793

Cited by 34 publications

(13 citation statements)

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“…CMOS Switch for Buck DC-DC Converter 3.1 Schrom's CMOS switch design method G. Schrom et al 7) reported an optimal design of the CMOS switch used in a buck DC-DC converter. Fig.…”

Section: Zn-fe Ferrite Thick Film Deposited On Polyimide Under-layermentioning

confidence: 99%

CMOS Switch Buck DC-DC Converter Fabricated in Organic Interposer with Embedded Zn-Fe Ferrite Core Inductor

et al. 2015

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To achieve a package-level DC power grid for the next-generation power delivery to LSIs, multiple point-of-load (POL) buck DC-DC converters must be integrated into the package. We developed a 180 nm CMOS switch DC-DC buck converter for the POL DC power supply using a Zn-Fe ferrite core planar inductor embedded in an organic interposer. The embedded inductor had a 25 m thick copper spiral coil sandwiched by 10 m thick Zn-Fe ferrite thick film fabricated using the spin-spray method, which exhibited an inductance of 4.6 nH and a Q-factor of 11 at 50 MHz. A 180 nm CMOS switch was mounted using a flip-chip scheme on the organic interposer with the embedded inductor. The developed 50 MHz switching CMOS switch buck DC-DC converter exhibited a power conversion efficiency of about 68% when the input voltage was 2 V, the on-duty ratio was 0.5, the output voltage was 0.855 V, and the current was 1 A.

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“…CMOS Switch for Buck DC-DC Converter 3.1 Schrom's CMOS switch design method G. Schrom et al 7) reported an optimal design of the CMOS switch used in a buck DC-DC converter. Fig.…”

Section: Zn-fe Ferrite Thick Film Deposited On Polyimide Under-layermentioning

confidence: 99%

CMOS Switch Buck DC-DC Converter Fabricated in Organic Interposer with Embedded Zn-Fe Ferrite Core Inductor

et al. 2015

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“…Equation (10) is intractable in f. If the skin effect is neglected, R ac = 0, making the solution of (10) the same as in [4],…”

Section: Optimization Of Switching Frequencymentioning

confidence: 99%

“…Therefore, at light loads, the efficiency of the converter significantly drops and may fall below an acceptable range. Area scaling methods to improve the efficiency at light loads are proposed in [4] and [10]. Modern integrated circuits, such as microprocessors or chipsets, exhibit high dynamic range of the load current ranging from 50 mA to 1.5 A. Optimization for light loads is therefore critical.…”

Section: Optimization For Light Loadmentioning

confidence: 99%

“…Area scaling is performed by disabling portions of the power stage. In [4], the switching frequency remains constant when area scaling is performed. Based on the switching frequency optimization method illustrated in Fig.…”

Section: Optimization For Light Loadmentioning

confidence: 99%

“…A buck converter needs to operate at high switching frequencies (hundreds of MHz) for the inductor to be sufficiently small. Existing work on analytic modeling of integrated DC-DC converter efficiency [2][3][4][5] does not properly address the combination of high switching frequencies and air-core inductors. Consequently, a need for considering high frequency effects, such as the skin effect, arises.…”

Section: Introductionmentioning

confidence: 99%

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Efficiency optimization of integrated DC-DC buck converters

Sizikov

Kolodny

Fridman

et al. 2010

2010 17th IEEE International Conference on Electronics, Circuits and Systems

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-An analytic method to evaluate frequency dependent losses in on-chip DC-DC buck converters is presented in this paper. Microprocessors or chipsets exhibit wide dynamic range of load current varying from 50mA up to 1.5 A per phase at full operation. Peak efficiency is shown to occur when the load current related losses and the inherent losses of the DC-DC converter are equal. Efficiency optimization methods are described for light and heavy load scenarios. The primary design objective is to maintain the load at the peak of the efficiency curve. A SPICE based circuit model of a DC-DC converter is applied to validate the proposed analytic methods.

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