Efficiency optimization of integrated DC-DC buck converters

Abstract

-An analytic method to evaluate frequency dependent losses in on-chip DC-DC buck converters is presented in this paper. Microprocessors or chipsets exhibit wide dynamic range of load current varying from 50mA up to 1.5 A per phase at full operation. Peak efficiency is shown to occur when the load current related losses and the inherent losses of the DC-DC converter are equal. Efficiency optimization methods are described for light and heavy load scenarios. The primary design objective is to maintain the load at the peak of the efficiency curve. A SPICE based circuit model of a DC-DC converter is applied to validate the proposed analytic methods.

An accurate CV-CC non-isolated buck battery charger using primary side PWM controller

“…The frequency of operation is optimized for reduction in power loss, so that the volume of the design is at its minimum. The rise in switching loss with frequency, and hyperbolic reduction of inductor losses [7] (for ≈ 24 • C temperature rise in inductor and 1A peak to peak ripple current) at the same time, are considered to arrive at the optimum switching frequency. This is found to be around 40kHz.…”

On-chip voltage regulator module (VRM) effect on power/ground noise and jitter at high-speed output buffer

“…Also, a heated die directly affects to the performance on dies with a RF/passive components which are sensitive to surround conditions. These days, on-chip VRM using same silicon technology for other power consumed IC and implemented on same silicon die has become on the rise [7][8][9][10][11][12][13]. Though passive components in on-chip VRM occupies a large area on die, its fast switching frequency and very low PDN impedance are attractive for high-speed digital IC.…”

“…Moreover, since a power loss at a switching circuit increase more under faster switching frequency, the power efficiency worsen at on-chip VRM. Thus, most reports mainly focus on more stable regulated voltage with low inductance and capacitance and higher power efficiency at fast switching frequency [12][13]. This paper introduces a basic on-chip VRM topology consisting of MOS switching model and LC filter model on PDN on high-speed output buffer.…”

Volume and efficiency optimization of a step-down DC/DC converter based on F-L-N parameters

“…Examination of the effect of interleaving on converter efficiency and volume may also serve the task of phase number optimization. Similar efficiency and power density oriented converter optimization approaches can be found in the literature [1]- [5]. Different optimization techniques are introduced and their effectiveness is compared in [1].…”