Optical Lithography Patterning of SiO<sub>2</sub> Layers for Interface Passivation of Thin Film Solar Cells

Bose, Sourav; Cunha, José M. V.; Suresh, Sunil; Wild, Jessica de; Lopes, Tomás S.; Barbosa, João R. S.; Silva, Ricardo; Borme, Jérôme; Fernandes, Paulo A.; Vermang, Bart; Salomé, Pedro M. P.

doi:10.1002/solr.201800212

Cited by 53 publications

(63 citation statements)

References 32 publications

(59 reference statements)

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“…There is also a more technologically viable technique to create these layers, which is DC sputtering. DC After the creation of the passivation layer, the thickness of this layer was determined using high angle annular dark-field (HAADF) transmission electron microscopy (TEM) in [9], spectrally resolved ellipsometry in [12,13,16,17,24,25], TEM in [14,18], energy dispersive X-ray spectroscopy (EDX) in [15], scanning electron microscopy (SEM) in [11,19,20,22], profilometry in [5], and atomic force microscopy (AFM) in [23]. The thickness of the passivation layer should be chosen to be sufficiently thin (~1-2 nm) to allow tunneling if there is no contact opening approach applied to this layer.…”

Section: Dielectric-based Passivation Layersmentioning

confidence: 99%

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Dielectric-Based Rear Surface Passivation Approaches for Cu(In,Ga)Se2 Solar Cells—A Review

et al. 2019

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This review summarizes all studies which used dielectric-based materials as a passivation layer at the rear surface of copper indium gallium (di)selenide, Cu(In,Ga)Se2, (CIGS)-based thin film solar cells, up to 2019. The results regarding the kind of dielectric materials, the deposition techniques, contacting approaches, the existence of additional treatments, and current–voltage characteristics (J–V) of passivated devices are emphasized by a detailed table. The techniques used to implement the passivation layer, the contacting approach for the realization of the current flow between rear contact and absorber layer, additional light management techniques if applicable, the solar simulator results, and further characterization techniques, i.e., external quantum efficiency (EQE) and photoluminescence (PL), are shared and discussed. Three graphs show the difference between the reference and passivated devices in terms of open-circuit voltage (Voc), short-circuit current (Jsc), and efficiency (η), with respect to the thicknesses of the absorber layer. The effects of the passivation layer at the rear surface are discussed based on these three graphs. Furthermore, an additional section is dedicated to the theoretical aspects of the passivation mechanism.

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Section: Dielectric-based Passivation Layersmentioning

confidence: 99%

“…To generate the contact openings in the Al 2 O 3 passivation layer, advanced techniques such as e-beam, nano-imprint, nano-sphere, or photolithography were used in the following studies [5,9,11,[16][17][18]22,23]. Lithography is one of the most advanced techniques that is used for this purpose.…”

Section: Contacting Approachmentioning

confidence: 99%

Dielectric-Based Rear Surface Passivation Approaches for Cu(In,Ga)Se2 Solar Cells—A Review

et al. 2019

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“…Several surface treatments, post‐deposition treatment (PDT) with an alkali metal, [ 14–21 ] the formation of a copper (Cu)‐deficient layer (CDL) on the CIGS surface, [ 5,13,22–24 ] and the interface passivation of CdS/CIGS with Al 2 O 3 , [ 25–28 ] have been used to improve the device performance of solar cells. PDT, such as potassium fluoride, modifies the CIGS surface (reduced gallium (Ga) concentration and depleted Cu), which allows the reduction of CdS thickness along with the maintenance of high efficiency.…”

Section: Introductionmentioning

confidence: 99%

Silver Surface Treatment of Cu(In,Ga)Se₂ (CIGS) Thin Film: A New Passivation Process for the CdS/CIGS Heterojunction Interface

Zhang

Lin

et al. 2020

Solar RRL

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The interface engineering of Cu(In,Ga)Se2 (CIGS)‐based solar cells is challenging for high‐efficiency devices, especially for the CdS/CIGS heterojunction interface. Recently, post‐treatment of the CIGS surface, as an efficient approach to passivate the defects at the CdS/CIGS interface, has attracted widespread attention. Here, a simple Ag surface treatment process is used to realize the passivation of interface defects and the enhancement of the CdS/CIGS heterojunction. This process not only reduces the surface roughness of CIGS films significantly, but also contributes to controlling the Ga composition in the surface layer. Furthermore, characterization techniques reveal that Ag surface treatment can effectively decrease the defect concentrations at the heterojunction interface and enhance the CdS/CIGS heterojunction quality with appropriate Ag deposition duration. Further investigations on the changed defect level caused by the Ag surface treatment indicate that the increased defect level is likely related to the shift of valence band maximum. Eventually, the efficiency of the optimum device has a relative increase of about 18% compared with that of the reference solar cell. This work focuses on revealing the differences of the CIGS surface and CdS/CIGS interface caused by Ag, which provides a new surface processing method for the passivation of the CdS/CIGS heterojunction.

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“…Optical lithography [24][25][26][27] is a parallel micro-/nanographic-imaging method that is commonly used in MEMS processing. In addition, etching process [28][29][30][31] is an important micro-/nanostructure process in MEMS and that is usually performed after lithography.…”

Section: Methodsmentioning

confidence: 99%

Experiment Research on Micro-/Nano Processing Technology of Graphite as Basic MEMS Material

Zhang

Liu

et al. 2019

Applied Sciences

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Graphite is expected to be a common choice for basic microelectromechanical-system (MEMS) material in the future. However, in order to become a basic MEMS material, it is very important for graphite to be adapted to the commonly-used micro-/nanoprocessing technology. Therefore, this paper used a directly lithography and etching process to study micro-, /nanoprocessing on graphite. The results show that the graphite surface is suitable for lithography, and that different shapes and sizes of photoresist patterns can be directly fabricated on the graphite surface. In addition, the micro-meter height of photoresist could still resist plasma etching when process nanometers height of graphite structures. Therefore, graphite with photoresist patterns were directly processed by etching, and nanometer amounts of graphite were etched. Moreover, micro-/nanoscale graphite structure with height ranges from 29.4 nm–30.9 nm were fabricated with about 23° sidewall.

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Optical Lithography Patterning of SiO₂ Layers for Interface Passivation of Thin Film Solar Cells

Cited by 53 publications

References 32 publications

Dielectric-Based Rear Surface Passivation Approaches for Cu(In,Ga)Se2 Solar Cells—A Review

Dielectric-Based Rear Surface Passivation Approaches for Cu(In,Ga)Se2 Solar Cells—A Review

Silver Surface Treatment of Cu(In,Ga)Se₂ (CIGS) Thin Film: A New Passivation Process for the CdS/CIGS Heterojunction Interface

Experiment Research on Micro-/Nano Processing Technology of Graphite as Basic MEMS Material

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Optical Lithography Patterning of SiO2 Layers for Interface Passivation of Thin Film Solar Cells

Cited by 53 publications

References 32 publications

Dielectric-Based Rear Surface Passivation Approaches for Cu(In,Ga)Se2 Solar Cells—A Review

Dielectric-Based Rear Surface Passivation Approaches for Cu(In,Ga)Se2 Solar Cells—A Review

Silver Surface Treatment of Cu(In,Ga)Se2 (CIGS) Thin Film: A New Passivation Process for the CdS/CIGS Heterojunction Interface

Experiment Research on Micro-/Nano Processing Technology of Graphite as Basic MEMS Material

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Optical Lithography Patterning of SiO₂ Layers for Interface Passivation of Thin Film Solar Cells

Silver Surface Treatment of Cu(In,Ga)Se₂ (CIGS) Thin Film: A New Passivation Process for the CdS/CIGS Heterojunction Interface