Optical link optimization using embedded forward error correcting codes

Abstract

Abstract-The design of a single-chip optical transceiver to optimize the performance of a short-distance optical datalink is proposed. The transceiver includes an embedded hybrid automatic repeat request (ARQ) controller capable of operation at several gigahertz clock rates. The hybrid ARQ controller uses a combination of packet retransmission protocols and forward error correction (FEC) to minimize bit errors and achieve a transmitter power coding gain of several dB. Conventional FEC codes such as Reed-Solomon codes cannot be used due to their excessive hardware cost and delays. A practical multilevel coding scheme is explored. The inner codes consist of small linear block codes with reasonable FEC capability, such as small BCH codes, which can be encoded and decoded with reasonable hardware cost and delay. The outer code for a complete packet consists of a long linear block code with excellent error detection ability, such as a cycle redundancy check code. Low-power pipelined on-chip FEC decoders with estimated throughputs of several hundred gigabits per second per square millimeter are proposed. Mathematical analysis indicates that substantial coding gains are possible, which can be used to increase the data rate or the distance span of the link. The proposed designs can be used in short-distance optical transceivers for 10-Gb ethernet, fiberchannel, and very short reach optical datalinks, and are scalable to future two-dimensional optical datalinks with Terabits of capacity.Index Terms-Automatic repeat request (ARQ), BCH, code, forward error correcting, optical link, pipelined, transceiver, very large scale integration.

Power complexity of multiplexer-based optoelectronic crossbar switches

“…Following the analysis in [39], the BER in the proposed system can be determined by assuming a thermal-noise limited system with white Gaussian noise, and the results are summarized. A receiver sensitivity of 16 dBm at 2 Gb/s, implies a BER of 10 , which further implies a signal-to-noise ratio (SNR) of 23 dB.…”

“…The power is given by (38) The latter two terms represent the input port and intrinsic capacitances of the DFF cell. The energy per bit switched (excluding the clock tree and memory) then becomes (39) The last term in the large bracket in (39) reflect the additional power consumed by the pipeline latches.…”