Optical Interface Platform for DRAM Integration

Ji, Ho-Chul; Ha, K. H.; Joe, In-Sung; Kim, S. G.; Na, K. W.; Shin, Dongjae; Suh, Sungsoo; Park, Y. D.; Chung, Chilhee

doi:10.1364/ofc.2011.othv4

Cited by 10 publications

(8 citation statements)

References 4 publications

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“…Recently, reports of solid phase epitaxy (SPE) silicon waveguides [18] and polysilicon waveguides [19] have demonstrated 6.1 dB/cm and 6.2 dB/cm propagation losses respectively in DRAM integrable platforms. The recently-proposed single-crystalline SPE silicon platform requires the deposition and recrystallization of an additional front-end layer to serve as a waveguide core.…”

Section: Introductionmentioning

confidence: 99%

“…The recently-proposed single-crystalline SPE silicon platform requires the deposition and recrystallization of an additional front-end layer to serve as a waveguide core. In addition to the cost of the additional layer, the yield of the fabricated devices may be coupled to the heterogeneous crystallization regions formed during SPE [18]. Although this approach may prove to be a valuable integration platform, we instead optimize the existing polysilicon layer present in the process as the transistor gate for use as an alternate low-optical loss waveguide core.…”

Section: Introductionmentioning

confidence: 99%

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Low-loss polysilicon waveguides fabricated in an emulated high-volume electronics process

Orcutt¹,

Tang²,

Kramer³

et al. 2012

Opt. Express

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We measure end-of-line polysilicon waveguide propagation losses of ~6-15 dB/cm across the telecommunication O-, E-, S-, C- and L-bands in a process representative of high-volume product integration. The lowest loss of 6.2 dB/cm is measured at 1550 nm in a polysilicon waveguide with a 120 nm x 350 nm core geometry. The reported waveguide characteristics are measured after the thermal cycling of the full CMOS electronics process that results in a 32% increase in the extracted material loss relative to the as-crystallized waveguide samples. The measured loss spectra are fit to an absorption model using defect state parameters to identify the dominant loss mechanism in the end-of-line and as-crystallized polysilicon waveguides.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Low-loss polysilicon waveguides fabricated in an emulated high-volume electronics process

Orcutt¹,

Tang²,

Kramer³

et al. 2012

Opt. Express

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show abstract

“…This constraint forbids the integration of standard single-crystalline silicon waveguides that have been previously demonstrated to provide low loss. Instead, deposited silicon waveguides suitable for integration within DRAM memory processes to enable photonic interconnect from processors to memory within future computation systems are being actively developed [10,11]. Polycrystalline silicon waveguides are desirable in this role as propagation losses below 10 dB/cm are achievable [12,13] using materials already common in such processes.…”

Section: Dram Integrationmentioning

confidence: 99%

Photonic Integration in State-of-the-Art Silicon Electronics Processes

Orcutt

2012

Advanced Photonics Congress

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“…Switching from electronic to optical CPU-MM buses that use novel fully functional all-optical interfaces for Dynamic Random Access Memory (DRAM) integration [3] has already proven beneficial. With current technology, fetching 256 bits of operand from the MM consumes more than 16 nJ [4].…”

Section: Introductionmentioning

confidence: 99%

High-Speed Optical Cache Memory as Single-Level Shared Cache in Chip-Multiprocessor Architectures

Maniotis

Gitzenis

Pleros

2015

2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing

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We present an optical bus-based Chip Multiprocessor architecture where the processing cores share an optical single-level cache unit. Physically, the optical cache is implemented externally in a separate chip located next to the CPU die. The cache interconnection system is realized through WDM optical interfaces that connect the shared cache module with the processing cores and the Main Memory via spatialmultiplexed optical waveguides; hence, the CPU-DRAM communication completely takes place in the optical domain. To evaluate the shared optical cache approach, we carry out systemlevel simulations of 6 realistic processor parallel workloads via the Gem5 platform. The optical cache architecture is compared against the conventional electronic Chip Multiprocessor topology that uses dedicated on-chip L1 electronic caches and a shared L2 cache. The results show significant reduction in the L1 miss rate of up to 96% for certain cases; on average, a performance speedup of up to 20.53% or a reduction of up to 65.8% in cache capacity requirements is attained. Combined with highbandwidth CPU-DRAM bus solutions based on optical interconnects, the proposed design is a quite promising system architecture that bridges the gap between high-speed optically connected CPU-DRAM schemes and high-speed optical memory technologies.

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Optical Interface Platform for DRAM Integration

Cited by 10 publications

References 4 publications

Low-loss polysilicon waveguides fabricated in an emulated high-volume electronics process

Low-loss polysilicon waveguides fabricated in an emulated high-volume electronics process

Photonic Integration in State-of-the-Art Silicon Electronics Processes

High-Speed Optical Cache Memory as Single-Level Shared Cache in Chip-Multiprocessor Architectures

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