Photonic Integration in State-of-the-Art Silicon Electronics Processes

Orcutt, Jason S.

doi:10.1364/iprsn.2012.im4a.2

Cited by 3 publications

(4 citation statements)

References 13 publications

(22 reference statements)

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“…3a and Extended Data Fig. 5), we selected two available Si MRMs realized in an electronic-photonic co-integration platform 63 . Si MRM device 1 (black curves) has a Q factor of 18,800 and 13.6 GHz FWHM 42 .…”

Section: Temperature Sensitivity Measurementsmentioning

confidence: 99%

Resonant plasmonic micro-racetrack modulators with high bandwidth and high temperature tolerance

et al. 2023

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Resonant modulators encode electrical data onto wavelength-multiplexed optical carriers. Today, silicon microring modulators are perceived as promising to implement such links; however, they provide limited bandwidth and need thermal stabilization systems. Here we present plasmonic micro-racetrack modulators as a potential successor of silicon microrings: they are equally compact and compatible with complementary-metal–oxide–semiconductor-level driving voltages, but offer electro-optical bandwidths of 176 GHz, a 28 times improved stability against operating temperature changes and no self-heating effects. The temperature-resistant organic electro-optic material enables operation at 85 °C device temperature. We show intensity-modulated transmission of up to 408 Gbps at 12.3 femtojoules per bit with a single resonant modulator. Plasmonic micro-racetrack modulators offer a solution to encode high data rates (for example, the 1.6 Tbps envisioned by next-generation communications links) at a small footprint, with low power consumption and marginal, if no, temperature control.

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Section: Temperature Sensitivity Measurementsmentioning

confidence: 99%

Resonant plasmonic micro-racetrack modulators with high bandwidth and high temperature tolerance

et al. 2023

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“…Concerning electronic-photonic design, Mentor Graphics [25] recently announced a collaboration with the photonic design and simulation companies PhoeniX Software and Lumerical Solutions [26]. Finally, Cadence ® has been utilised for designing photonic components by Luxtera, and has been utilised in our group since 2006 [27,28], however post-layout layer generation, automatic Manhattan discretisation, automatic DRC cleaning and photonic auto-routing had not been implemented.…”

Section: Photonic Design Tools State-of-the-artmentioning

confidence: 99%

Photonics design tool for advanced CMOS nodes

Alloatti

Wade

Stojanović

et al. 2015

IET Optoelectronics

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Recently, the authors have demonstrated large-scale integrated systems with several million transistors and hundreds of photonic elements. Yielding such large-scale integrated systems requires a design-for-manufacture rigour that is embodied in the 10 000 to 50 000 design rules that these designs must comply within advanced complementary metal-oxide semiconductor manufacturing. Here, the authors present a photonic design automation tool which allows automatic generation of layouts without design-rule violations. This tool is written in SKILL, the native language of the mainstream electric design automation software, Cadence. This allows seamless integration of photonic and electronic design in a single environment. The tool leverages intuitive photonic layer definitions, allowing the designer to focus on the physical properties rather than on technology-dependent details. For the first time the authors present an algorithm for removal of design-rule violations from photonic layouts based on Manhattan discretisation, Boolean and sizing operations. This algorithm is not limited to the implementation in SKILL, and can in principle be implemented in any scripting language. Connectivity is achieved with software-defined waveguide ports and low-level procedures that enable auto-routing of waveguide connections.Comment: 5 pages, 10 figure

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“…The channel spacing was set to 124 GHz with a 2 THz (16 nm) free spectral range. In interconnect applications, all wavelengths on a given waveguide are transmitted or received at a single location for all channels and travelling the same optical paths, so crosstalk requirements between channels is less restricted than in other telecommunications applications, being 20 dB a general accepted value [21]. Most of the second order filter bank designs based on SOI used radius of 7 μm in the manufactured devices and with projections to reduce those values to 3-4 μm.…”

Section: Circuit Designmentioning

confidence: 99%

“…Through port RR>-40 dB is obtained in all cases. These designs meet the target from medium to high bandwidth scenarios [21], [5], scaling up to 42 channels or 525 Gb/s with less post-fabrication trimming than current second-order filter designs, as it will be discussed in the next section. There is margin in the design values for accommodating 10% tolerances on coupling coefficients depending on the number of channels set.…”

Section: Circuit Designmentioning

confidence: 99%

Low power consumption silicon photonics tuning filters based on compound microring resonators

2013

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Scalable integrated optics platforms based on silicon-on-insulator allow to develop optics and electronics functions on the same chip. Developments in this area are fostered by its potential as an I/O technology that can meet the throughputs demand of future many-core processors. Most of the optical interconnect designs rely on small footprint and high power efficiency microring resonators. They are used to filter out individual channels from a shared bus guide. Second-order microring filters enable denser channel packing by having sharper pass-band to stop-band slopes. Taking advantage of using a single physical ring with clockwise and counter-clockwise propagation, we implement second order filters with lower tuning energy consumption as being more resilient to some fabrication errors. Cascade ability, remote stabilization potential, energy efficiency along with simple design equations on coupling coefficients are described. We design second-order filters with FWHM from 45 GHz to 20 GHz, crosstalk between channels from -40 dB to -20 dB for different channel spacing at a specific FSR, with energy efficiencies of single ring configurations and compatible with silicon-on-insulator (SOI) state of the art platforms.

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Photonic Integration in State-of-the-Art Silicon Electronics Processes

Cited by 3 publications

References 13 publications

Resonant plasmonic micro-racetrack modulators with high bandwidth and high temperature tolerance

Resonant plasmonic micro-racetrack modulators with high bandwidth and high temperature tolerance

Photonics design tool for advanced CMOS nodes

Low power consumption silicon photonics tuning filters based on compound microring resonators

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