Opportunities for harmonic cancellation with carrier-based PWM for a two-level and multilevel cascaded inverters

Holmes, D.G.; McGrath, Brendan

doi:10.1109/28.913724

Cited by 315 publications

(99 citation statements)

References 5 publications

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“…The frequency-spectra characteristic analysis of the pulse-width modulation (PWM) process has been reported in Holmes & McGrath (2001), where the phase voltage can be expressed in the following form:…”

Section: Proposed Methodsmentioning

confidence: 99%

New grid impedance estimation technique for grid-connected power converters

Guo

Sun

et al. 2014

J Engin Res

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Grid impedance estimation is crucial for operating and controlling of grid-connected converters, especially with the high penetration of renewable energy sources into microgrid and smart grid. One of the technical challenges is how to fast and accurately estimate the grid impedance, even under the distorted and unbalanced conditions. Many impedance estimation methods have been presented in the past decades. Most of them intentionally inject one or more disturbance signals, low frequency or high frequency, to excite the grid response. And then the grid impedance can be estimated by the voltage/current information of two steady-state operating points before and after the disturbance. However, these injected disturbances will deteriorate the power quality due to harmonics caused by the injected disturbances. In order to mitigate the problem, a new impedance estimation method is presented in this paper. Its basic idea lies in the inherent switching feature of the grid-connected power converter. The unique feature is that the proposed new grid impedance can be easily estimated, even under distorted and unbalanced grid voltage conditions with no need of the intentionally injected disturbance signals any more. First of all, the system equivalent impedance circuit is analyzed to clarify the proposed method, along with a theoretical comparison with the conventional one. Aside from that, an interesting estimation of voltage and current switching components are presented for determining the grid impedance with two well-defined equations. And then, the performance tests are carried out and the results verify the effectiveness of the proposed method. Finally, a typical application of the proposed method is presented and discussed.

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Section: Proposed Methodsmentioning

confidence: 99%

New grid impedance estimation technique for grid-connected power converters

Guo

Sun

et al. 2014

J Engin Res

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“…There are nine sufficient switching modes in generating the multistep level for a 9-level MLI. There are four different pulse width modulation strategies as given below [14][15][16].…”

Section: Opertion Of the Proposed Topology Using 9-level Acmlimentioning

confidence: 99%

THD Minimization Based Asymmetrical Cascade Multilevel Inverter with Different Modulation Techniques

Sharma¹,

Kaurav²

2018

IJERT

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“…Other than the POD-SPWM, there are two more Alternative Carrier Disposition SPWM strategies commonly used in switching technique that applied in control strategy. These are (i) Phase Disposition (PD), where all carriers are in phase [6] and (ii) Alternate Phase Opposition Disposition (APOD), where each carrier is phase shifted by π from its adjacent carrier. In addition, abundant modulation techniques and control paradigm have been developed for various levels of pulse width modulation converters other than sinus (SPWM).…”

Section: Introductionmentioning

confidence: 99%

Seven Levels Symmetric H-bridge Multilevel Inverter with Less Number of Switching Devices

Chulan¹,

Aziz²,

Yatim³

et al. 2017

IJPEDS

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This paper proposes a new topology of a cascaded multilevel inverter that utilises less number of switches than the conventional topology. The proposed topology maintains the performance of conventional 7-levels output multilevel inverter while reducing the loss of power, installation area, converter size as well as development cost. The circuit development consists of six switches and one diode. With less number of switching devices in the circuit, there will be a reduction in the gate driver circuits and also in effect fewer switches required for specific intervals of time. Simulation works have been conducted to validate the proposed MLI topology. It is envisaged that the proposed topology can be applied for the system that requires high efficiency and a low electromagnetic interference. Keyword: Copyright © 2017 Institute of Advanced Engineering and Science.All rights reserved. Corresponding Author:Megat Azahari Chulan, Faculty of Electrical and Electronics Engineering, Universiti Tun Hussein Onn Malaysia (UTHM), Malaysia. Email: megat@uthm.edu.my INTRODUCTIONMultilevel inverters (MLI) are popular converter topologies due to the operational abilities of a high-voltage, high efficiency and a low electromagnetic interference [1]. Despite the many researches carried out in this configuration, MLI still evolves. Multilevel inverter is used to maintain a low harmonics in the operating system and reducing the switching stress and thus improving the converter efficiency. Normally, in order to achieve that objective, the number of the voltage source and switching operation are increased. However, the loss of power and the cost of converter development would significantly increase. Thus, there is a need for the current MLI topologies evolution to concentrate on those issues. Reducing the number of components, applying advance control strategies and switching algorithm to ensure the converter's output quality can be increased are some of the modifications made to tackle the issues.Although THD performance is enhanced, the complexity in its control circuit due to the high number of semiconductor switches introduces high switching and conduction losses. Considering these issues, several new and improved multilevel inverter topologies have been introduced as discussed in [2], [3]. The authors have suggested a design methodology to synthesize multilevel inverter output with a large number of levels with good spectral performance but with a reduced number of switches. Various topologies of multilevel inverter have also been proposed focusing on the reduced number of switches and components and at the same time maintaining the quality of the converter output voltage as well as cost of installation reduction.Conventional 7 levels Cascaded Multilevel Inverters (CMLI) requires 12 switches and three DC sources. In fact, early research in [5] has managed to reduce the number of switches to 9 with the desired

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Opportunities for harmonic cancellation with carrier-based PWM for a two-level and multilevel cascaded inverters

Cited by 315 publications

References 5 publications

New grid impedance estimation technique for grid-connected power converters

New grid impedance estimation technique for grid-connected power converters

THD Minimization Based Asymmetrical Cascade Multilevel Inverter with Different Modulation Techniques

Seven Levels Symmetric H-bridge Multilevel Inverter with Less Number of Switching Devices

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