Operation and stability analysis of bipolar OxRRAM-based Non-Volatile 8T2R SRAM as solution for information back-up

Hraziia,; Makosiej, Adam; Palma, Giorgio; Portal, Jean‐Michel; Bocquet, Marc; Thomas, Olivier; Clermidy, Fabien; Reyboz, Marina; Onkaraiah, Santhosh; Müller, Christophe; Deleruyelle, Damien; Vladimirescu, Andrei; Amara, Amara; Anghel, Costin

doi:10.1016/j.sse.2013.02.045

Cited by 5 publications

(7 citation statements)

References 21 publications

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“…2. Specific RESET-SET sequence prevent redundant writes thereby, improving the endurance of RRAMs at the circuit-level [3]. In 6T-NVSRAM cell configuration, specialized memories of both volatile and non-volatile are required in order to be compatible especially in terms of voltage.…”

Section: Operation Sequence and Working Principlementioning

confidence: 99%

“…At present, it is not possible to replace the SRAMs only with RRAMs mainly due to two reasons: (i) RRAMs are slower (~5ns) than SRAMs (ii) RRAMs have lower endurance (10 12 cycles) than SRAMs (10 16 ). Hence, over the years, the solution proposed to replace SRAMs is a hybrid of both the volatile and non-volatile technologies widely known as Non-Volatile SRAMs (NVSRAMs) [1][2][3]. This type of hybrid architecture can work as fast as the SRAMs by using SRAMs during the active mode and the RRAMs to retain the SRAMs contents during the idle mode or power-down mode.…”

Section: Introductionmentioning

confidence: 99%

“…The NVSRAMs found in the literature have the emerging NVMs integrated (i) as part of SRAMs by connecting it to the SRAM data nodes [2,3] or (ii) as part of SRAM latch [2] or (iii) between the SRAM data nodes and the bitlines [1]. The NVSRAM (Fig.…”

Section: Introductionmentioning

confidence: 99%

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Design challenges and solutions for Non-Volatile SRAMs

Hraziia

Vladimirescu

Anghel

et al. 2014

2014 IEEE Faible Tension Faible Consommation

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Section: Operation Sequence and Working Principlementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Design challenges and solutions for Non-Volatile SRAMs

Hraziia

Vladimirescu

Anghel

et al. 2014

2014 IEEE Faible Tension Faible Consommation

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“…In this paper, we focus on the power ON/OFF application using the novel NVSRAM memory with bipolar OxRRAM technology [21] to store and restore the bitstream quickly in a power on/off cycle. We can achieve a total power down state i.e.…”

Section: IImentioning

confidence: 99%

“…The NVSRAM cell used for this work makes use of the NVSRAM cell architecture and operating principle proposed in [21]. Two OxRRAM devices (R 1 , R 2 ) are used per SRAM cell (M1-M6).…”

Section: ) Memory Cell Architecturementioning

confidence: 99%

RRAM-based FPGA for "normally off, instantly on" applications

Turkyilmaz

Onkaraiah

Reyboz

et al. 2012

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures

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Normally off, instantly on" applications are becoming common in our environment. They range from healthcare to video surveillance. As the number of applications and their associated performance requirements grow rapidly, more and more powerful, flexible and power efficient computing units are necessary. In such a context, Field Programmable Gate Arrays (FPGA) architectures present a good trade-off between performance and flexibility. However, they consume high static power and can hardly be associated with power gating techniques due to their long context restoring phase. In this paper, we propose to integrate non-volatile resistive memories in configuration cells in order to instantly restore the FPGA context. We then show that if the circuit is in 'ON' state for less than 42% of time, non-volatile FPGA starts saving energy compared to classical FPGA. Finally, for a typical application with only 1% of time spent in 'ON' state, the energy gain reaches 50%.

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A CMOL-Like Memristor-CMOS Neuromorphic Chip-Core Demonstrating Stochastic Binary STDP

Camuñas-Mesa

Vianello

Reita

et al. 2022

IEEE J. Emerg. Sel. Topics Circuits Syst.

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The advent of nanoscale memristors raised hopes of being able to build CMOL (CMOS/nanowire/molecular) type ultra-dense in-memory-computing circuit architectures. In CMOL, nanoscale memristors would be fabricated at the intersection of nanowires. The CMOL concept can be exploited in neuromorphic hardware by fabricating lower density neurons on CMOS and placing massive analog synaptic connectivity with nanowire and nanoscale-memristor fabric post-fabricated on top. However, technical problems have hindered such developments for presently available reliable commercial monolithic CMOSmemristor technologies. On one hand, each memristor needs a MOS selector transistor in series to guarantee forming and programming operations in large arrays. This results in compound MOS-memristor synapses (called 1T1R) which are no longer synapses at the crossing of nanowires. On the other hand, memristors do not yet constitute highly reliable, stable analog memories for massive analog-weight synapses with gradual learning. Here we demonstrate a pseudo-CMOL monolithic chip core that circumvents the two technical problems mentioned above by: (a) exploiting a CMOL-like geometrical chip layout technique to improve density despite the 1T1R limitation, and (b) exploiting a binary weight stochastic Spike-Timing-Dependent-Plasticity (STDP) learning rule that takes advantage of the more reliable binary memory capability of the memristors used. Experimental results are provided for a spiking neural network (SNN) CMOL-core with 64 input neurons, 64 output neurons and 4096 1T1R synapses, fabricated in 130nm CMOS with 200nm-sized Ti/HfOx/TiN memristors on top. The CMOL-core uses query-driven event read-out, which allows for memristor variability insensitive computations. Experimental system-level demonstrations are provided for plain template matching tasks, as well as regularized stochastic binary STDP feature-extraction learning, obtaining perfect recognition in hardware for a 4-letter recognition experiment.

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Operation and stability analysis of bipolar OxRRAM-based Non-Volatile 8T2R SRAM as solution for information back-up

Cited by 5 publications

References 21 publications

Design challenges and solutions for Non-Volatile SRAMs

Design challenges and solutions for Non-Volatile SRAMs

RRAM-based FPGA for "normally off, instantly on" applications

A CMOL-Like Memristor-CMOS Neuromorphic Chip-Core Demonstrating Stochastic Binary STDP

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