OPC simplification and mask cost reduction using regular design fabrics

Jhaveri, Tejas; Stobert, Ian; Liebmann, Lars W.; Karakatsanis, Paul; Rovner, Vyacheslav; Strojwas, Andrzej J.; Pileggi, Larry

doi:10.1117/12.814406

Cited by 17 publications

(8 citation statements)

References 8 publications

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“…In addition to being design-efficient, the 9T_UniDir still lives up to its promise of lower manufacturing cost by having simpler and fewer constructs and saving one exposure in the M1 level. The simpler and fewer constructs lead to lower process risk, lower mask costs and better process optimization [9]. After systematic and rigorous assessment of standard cells for design efficiency and manufacturability, 9T_UniDir emerges as the preferred cell library of choice.…”

Section: Discussionmentioning

confidence: 99%

<title>Design and manufacturability tradeoffs in unidirectional and bidirectional standard cell layouts in 14 nm node</title>

Vaidyanathan

Morris

et al. 2012

Design for Manufacturability Through Design-Process Integration VI

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The 14 nm node is seeing the dominant use of three-dimensional FinFET architectures, local interconnects, multiple patterning processes and restricted design rules. With the adoption of these new process technologies and design styles, it becomes necessary to rethink the standard cell library design methodologies that proved successful in the past. In this paper, we compare the design efficiency and manufacturability of standard cell libraries that use either unidirectional or bidirectional Metal 1. In contrast to previous nodes, a 14 nm 9-track unidirectional standard cell layout results in up to 20% lower energy-delay-area product as compared to the 9-track bidirectional standard cell layout. Manufacturability assessment shows that the unidirectional standard cell layouts save one exposure on Metal 1, reduces process variability by 10% and layout construct count by 2-3X. As a result, the unidirectional standard cell layout could serve as a key enabler for affordable scaling.

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Section: Discussionmentioning

confidence: 99%

<title>Design and manufacturability tradeoffs in unidirectional and bidirectional standard cell layouts in 14 nm node</title>

Vaidyanathan

Morris

et al. 2012

Design for Manufacturability Through Design-Process Integration VI

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“…This is in fact a DFM technique that is increasingly being used in practice to allow more critical dimension (CD) control over transistors. This regularization can also be used to simplify the OPC recipe for transistors [16]. Additionally, it allows the use of simpler models in place of full lithography simulation to model process window of transistors [13,16].…”

Section: Timing-driven Cost Function For Optical Proximity Corrementioning

confidence: 98%

“…This regularization can also be used to simplify the OPC recipe for transistors [16]. Additionally, it allows the use of simpler models in place of full lithography simulation to model process window of transistors [13,16]. It has previously been shown that feature CD shows a linear dependence on dose errors (∆d) and is modeled using the image log slope (ILS) (Eq.…”

Section: Timing-driven Cost Function For Optical Proximity Corrementioning

confidence: 99%

Coupling timing objectives with optical proximity correction for improved timing yield

Banerjee

Agarwal

Nassif

et al. 2011

2011 12th International Symposium on Quality Electronic Design

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Design-manufacturing co-optimization has been earmarked as a key enabler of future technology scaling. Current manufacturing methods treat all transistors equally irrespective of their criticality in the design flow. In the presence of variations in the lithographic process, this leads to timing violations which reduces chip yield. In this paper, we develop a timing-driven process window optical proximity correction (TD-PWOPC) algorithm that tunes the mask generation for each transistor based on its electrical criticality in the design. Our method utilizes knowledge of timing information to generate delay bounds on each cell. It then develops a process variation aware OPC cost function for each cell to ensure that post-lithography delay lies within these bounds. This method uses a single image simulation coupled with simplified models for regular polysilicon layouts to predict though-process performance. We finally use a gradient-descent algorithm to minimize this cost function. Results show that the use of TD-PWOPC can reduce delay errors significantly compared to regular OPC at small runtime overheads of 4.5%.

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“…One derived advantage is the improved process windows due to a simpler RET solution because of more regular designs. A simpler OPC [47] and a reduced number of hotspots are possible as shown in Figure 26 . Much fewer constructs are needed for the designers to construct standard cell designs for unidirectional designs [48,49] .…”

Section: Ultimate Design For Scalingmentioning

confidence: 99%

Review of computational lithography modeling: focusing on extending optical lithography and design-technology co-optimization

Lai

2012

Advanced Optical Technologies

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Advances in computational lithography over the last 10 years have been instrumental to the continued scaling of semiconductor devices. Competitive scaling requires two types of complementary models: fast predictive empirical models that can be used for pattern correction and verification; rigorous physical models that can be used to identify key physical effects that must be considered to ensure pattern fidelity, but are too resource intensive to use for full chip applications. Today, all computational lithography efforts such as the optical proximity correction (OPC) and the optical rules check (ORC) depend on the ability to predictively model the lithography and metrology processes. We discuss some of the current modeling practices in optics, mask, resist and etching, leading to the " Holy Grail " of predictively modeling entire patterning process which we call " virtual fab " . Extreme ultraviolet (EUV) modeling is discussed due to its potential to extend optical lithography scaling for future nodes. Modeling of novel technologies such as Diblock Copolymer patterning is also discussed to demonstrate new opportunities for continued scaling. Complexity of the " virtual fab " approach is extremely high as there are multiple dimensions in this approach. The need to overcome this complexity, by reducing the number of dimensions of the problem, is evident. Lastly, the ability to leverage lithography modeling in design co-optimization is an important element of semiconductor device scaling.

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OPC simplification and mask cost reduction using regular design fabrics

Cited by 17 publications

References 8 publications

<title>Design and manufacturability tradeoffs in unidirectional and bidirectional standard cell layouts in 14 nm node</title>

<title>Design and manufacturability tradeoffs in unidirectional and bidirectional standard cell layouts in 14 nm node</title>

Coupling timing objectives with optical proximity correction for improved timing yield

Review of computational lithography modeling: focusing on extending optical lithography and design-technology co-optimization

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