On the VLSI implementation of the international data encryption algorithm IDEA

Wolter, S.; Matz, H.; Schubert, Andreas; Laur, R.

doi:10.1109/iscas.1995.521534

Cited by 27 publications

(12 citation statements)

References 7 publications

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“…Zimmermann (1994) 8 stage pipeline used Efficient but incompatible for high speed network applications. Wolter (1995) 10 stage pipeline used Additional area requirements due to on chip data management. Salomao (1998) RAMs were used for storing subkeys Unable to work with multiple keys.…”

Section: Comparison and Analysismentioning

confidence: 99%

A Survey on Hardware Implementation of IDEA Cryptosystem

Mukherjee

Sahoo

2011

Information Security Journal: A Global Perspective

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The main goal of hardware implementation of a cryptosystem is to make it compatible for high speed networks. The cryptographic algorithms are very much computationally intensive and to achieve a high speed execution, hardware is necessary. In this paper, various hardware implementations of the IDEA cipher is discussed. The hardware implementation involves both ASIC and FPGA implementations and IDEA has been implemented quite a several times in hardware. But a complete survey of all the previous implementations has not been presented before. In each of these implementations, the focus has been made on the data throughput, area requirements and the architecture of the algorithm proposed.

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Section: Comparison and Analysismentioning

confidence: 99%

A Survey on Hardware Implementation of IDEA Cryptosystem

Mukherjee

Sahoo

2011

Information Security Journal: A Global Perspective

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“…al. [24] presented an implementation of the IDEA algorithm in which data are first encrypted and then, as a check, decrypted with the result compared to the original plaintext. Public key algorithms are analyzed in [8], where the authors propose an approach for providing error detection and correction by means of redundant arithmetic based on finite rings.…”

Section: Related Workmentioning

confidence: 99%

Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?

Regazzoni

Eisenbarth²,

Breveglieri

et al. 2008

2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems

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Side-channel attacks are nowadays a serious concern when implementing cryptographic algorithms. Powerful ways for gaining information about the secret key as well as various countermeasures against such attacks have been recently developed. Although it is well known that such attacks can exploit information leaked from different sources, most prior works have only addressed the problem of protecting a cryptographic device against a single type of attack. Consequently, there is very little knowledge on how a scheme for protecting a device against one type of side-channel attack may affect its vulnerability to other types of side-channel attacks. In this paper we focus on devices that include protection against fault injection attacks (using different error detection schemes) and explore whether the presence of such fault detection circuits affects the resistance against attacks based on power analysis. Using the AES S-Box as an example, we performed attacks on the unprotected implementation as well as modified implementations with parity check circuits or residue check circuits (mod3 and mod7). In particular, we focus on the question whether the knowledge of the presence of error detection circuitry in the cryptographic device can help an attacker who attempts to mount a power attack on the device. Our results show that the presence of error detection circuitry helps the attacker even if he is unaware of this circuitry, and that the benefit to the attacker increases with the number of check bits used for the purpose of error detection.

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“…al. [13] developed a CED technique for symmetric block cipher IDEA wherein the test data was encrypted and then decrypted. This approach entails more than 100% time overhead.…”

Section: Ced Architectures For Symmetric Block Ciphers: Backgroundmentioning

confidence: 99%

“…al. [13] used residue codes for fault detection in adders, multipliers, and EXCLUSIVE-ORs. Area overhead of this approach is due to the encoders at the input and decoders at the output to translate the plain and cipher texts into the internal code words.…”

Section: Ced Architectures For Symmetric Block Ciphers: Backgroundmentioning

confidence: 99%

Parity-Based Concurrent Error Detection of Substitution-Permutation Network Block Ciphers

Karri¹,

Kuznetsov

Goessel

2003

Lecture Notes in Computer Science

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Abstract. Deliberate injection of faults into cryptographic devices is an effective cryptanalysis technique against symmetric and asymmetric encryption algorithms. In this paper we will describe parity code based concurrent error detection (CED) approach against such attacks in substitution-permutation network (SPN) symmetric block ciphers [22]. The basic idea compares a carefully modified parity of the input plain text with that of the output cipher text resulting in a simple CED circuitry. An analysis of the SPN symmetric block ciphers reveals that on one hand, permutation of the round outputs does not alter the parity from its input to its output. On the other hand, exclusive-or with the round key and the non-linear substitution function (s-box) modify the parity from their inputs to their outputs. In order to change the parity of the inputs into the parity of outputs of an SPN encryption, we exclusive-or the parity of the SPN round function output with the parity of the round key. We also add to all s-boxes an additional 1-bit binary function that implements the combined parity of the inputs and outputs to the s-box for all its (input, output) pairs. These two modifications are used only by the CED circuitry and do not impact the SPN encryption or decryption. The proposed CED approach is demonstrated on a 16-input, 16-output SPN symmetric block cipher from [1].

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On the VLSI implementation of the international data encryption algorithm IDEA

Cited by 27 publications

References 7 publications

A Survey on Hardware Implementation of IDEA Cryptosystem

A Survey on Hardware Implementation of IDEA Cryptosystem

Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?

Parity-Based Concurrent Error Detection of Substitution-Permutation Network Block Ciphers

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