Parity-Based Concurrent Error Detection of Substitution-Permutation Network Block Ciphers

Abstract

Abstract. Deliberate injection of faults into cryptographic devices is an effective cryptanalysis technique against symmetric and asymmetric encryption algorithms. In this paper we will describe parity code based concurrent error detection (CED) approach against such attacks in substitution-permutation network (SPN) symmetric block ciphers [22]. The basic idea compares a carefully modified parity of the input plain text with that of the output cipher text resulting in a simple CED circuitry. An analysis of the SPN symmetric block ciphers reveals that on one hand, permutation of the round outputs does not alter the parity from its input to its output. On the other hand, exclusive-or with the round key and the non-linear substitution function (s-box) modify the parity from their inputs to their outputs. In order to change the parity of the inputs into the parity of outputs of an SPN encryption, we exclusive-or the parity of the SPN round function output with the parity of the round key. We also add to all s-boxes an additional 1-bit binary function that implements the combined parity of the inputs and outputs to the s-box for all its (input, output) pairs. These two modifications are used only by the CED circuitry and do not impact the SPN encryption or decryption. The proposed CED approach is demonstrated on a 16-input, 16-output SPN symmetric block cipher from [1].

Differential Fault Analysis Attack Resistant Architectures for the Advanced Encryption Standard

“…Several methods for protection of AES have been developed. However, the current methods do not provide an adequate solution since they either require duplication in time or space [9], or they are not effective for all fault attacks [10,11].…”

Side-channel power analysis of different protection schemes against fault attacks on AES

“…To protect cryptographic devices from such DFA attacks or improve the reliability of the system, many fault detection and correction schemes have been presented [1,7,8,9,10,11,12,13,14,15,16,17]. Some of them exploit the algebraic feature of the cryptographic algorithms.…”

Design and implementation of robust embedded processor for cryptographic applications

“…Also, error detection codes can be used to detect the data errors which are either maliciously introduced by adversary or naturally occurred. For example, the works [2,11,10] propose simple error detection schemes using parity bits for the symmetric cipher implementations. Also, the works [14,15] add simple error detection circuits into finite field multipliers to detect faulty computations.…”