A Survey on Hardware Implementation of IDEA Cryptosystem

Abstract

The main goal of hardware implementation of a cryptosystem is to make it compatible for high speed networks. The cryptographic algorithms are very much computationally intensive and to achieve a high speed execution, hardware is necessary. In this paper, various hardware implementations of the IDEA cipher is discussed. The hardware implementation involves both ASIC and FPGA implementations and IDEA has been implemented quite a several times in hardware. But a complete survey of all the previous implementations has not been presented before. In each of these implementations, the focus has been made on the data throughput, area requirements and the architecture of the algorithm proposed.

SPD-Safe: security, privacy and dependability management on embedded systems in safety-critical applications

“…Yet, IDEA performs well in embedded software and is used in PGP v2.0. Its most compact implementation occupies 596 bytes of code for 94.8 Kbps throughput [237]. Similarly to AES, biclique attacks are slightly faster than exhaustive search [238].…”