On The Use Of N-well Resistors For Uniform Triggering Of Esd Protection Elements

Notermans, Guido

doi:10.1109/eosesd.1997.634246

Cited by 24 publications

(11 citation statements)

References 10 publications

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“…Moreover, there is a second snapback around the current level of 0.6A. The observed second snapback is related to the second snapback inside the N-Well [5]. While the TLP pulse energy increases step by step, the N+/P-Well junction breaks down and triggers on the parasitic np-n BJT.…”

Section: Resultsmentioning

confidence: 86%

“…To improve the ESD robustness of fully-silicided NMOS, an N-Well covers the drain side to increase the ballast resistance and to preserve the driving capability of the NMOS. With the high sheet resistance of N-Well, the N-Well ballast structure has been reported to effectively increase ESD robustness of CMOS ICs [5]- [6], [12].…”

Section: Introductionmentioning

confidence: 99%

“…However, additional process steps and mask layer for the SB increase the cost for production. To maintain enough ballast resistance for ESD protection NMOS without using the SB, several ballasting designs have been proposed [5]- [9]. In addition to the lowered ballast resistance of fully-silicided NMOS, asymmetry of parasitic substrate resistances (Rsub) among fingers of ESD protection NMOS has been recognized as another factor to limit ESD robustness of ESD protection NMOS [10], [11].…”

Section: Introductionmentioning

confidence: 99%

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A bending N-Well ballast layout to improve ESD robustness in fully-silicided CMOS technology

Wen

Ker

Chen

2010

2010 IEEE International Reliability Physics Symposium

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Ballast technique has been reported as a cost effective method to improve ESD robustness of fully-silicided devices without using silicide block. In this work, a new ballast technique, the bending NWell (BNW) ballast structure, is proposed to enhance ESD robustness of fully-silicided NMOS. With a deep N-Well to cover the fully-silicided NMOS with BNW ballast structure, ESD robustness of the NMOS can be further improved by enhancing the turn-on uniformity among the multi-fingers of the NMOS.

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Section: Resultsmentioning

confidence: 86%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A bending N-Well ballast layout to improve ESD robustness in fully-silicided CMOS technology

Wen

Ker

Chen

2010

2010 IEEE International Reliability Physics Symposium

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“…This technique uses N-Well resistor for the ballasting to ensure simultaneous triggering of multi-fingers and to avoid current crowding [5,11]. However, careless use of an n-well resistor in the drain of GGNMOS may reduce the ESD performance significantly because of the snap-back of n-well resistor itself.…”

Section: N-well Resistormentioning

confidence: 99%

<title>ESD protection design for advanced CMOS</title>

Huang¹,

Wang²

2001

SPIE Proceedings

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ESD effects in integrated circuits have become a major concern as today's technologies shrink to sub-micron/deep-submicron dimensions. The thinner gate oxide and shallower junction depth used in the advanced technologies make them very vulnerable to ESD damages. The advanced techniques like silicidation and STI (shallow trench insulation) used for improving other device performances make ESD design even more challenging. For non-silicided technologies, a certain DCGS (drain contact to gate edge spacing) is needed to achieve ESD hardness for nMOS output drivers and nMOS protection transistors. The typical DCGS values are 4-5um and 2-3um for 0.5um and 0.25um CMOS, respectively. The silicidation reduces the ballast resistance provided by DCGS with at least a factor of 10. As a result, scaling of the ESD performance with device width is lost and even zero ESD performance is reported for standard silicided devices.The device level ESD design is focused in this paper, which includes GGNMOS (gate grounded NMOS) and GCNMOS (gate coupled NMOS). The device level ESD testing including TLP (transmission line pulse) is given. Several ESD issues caused by advanced technologies have been pointed out. The possible solutions have been developed and summarized including silicide blocking, process optimization, back-end ballasting, and new protection scheme, dummy gate/n-well resistor ballsting, etc. Some of them require process cost increase, and others provide novel, compact, and simple design but involving royalty/IP (intellectual property) issue. Circuit level ESD design and layout design considerations are covered. The top-level ESD protection strategies are also given.

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“…However, if low-resistive lines that are common in highfrequency designs are used [2]- [4], [7], the voltage drop due to metal line ohmic heating during the ESD event could be minimal [8], [9]. A small resistor in series with the ESD devices could further improve the snap-back triggering uniformity [10].…”

Section: Distributed Esd Designmentioning

confidence: 99%

Distributed ESD protection for high-speed integrated circuits

Kleveland¹,

Maloney

Morgan

et al. 2000

IEEE Electron Device Lett.

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Abstract-Conventional ESD guidelines dictate a large protection device close to the pad. The resulting capacitive load causes a severe impedance mismatch and bandwidth degradation. A distributed ESD protection scheme is proposed to enable a low-loss impedance-matched transition from the package to the chip. A simple resistive model adequately predicts the ESD behavior under stress according to the charged device and human body models. The large area of the distributed ESD scheme would limit its application to designs such as distributed amplifiers, rf transceivers, A/D converters, and serial links with only a few dedicated high-speed interfaces. The distributed ESD protection is compatible with high-speed layout guidelines, requiring only low-loss transmission lines in addition to a conventional ESD device.

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On The Use Of N-well Resistors For Uniform Triggering Of Esd Protection Elements

Cited by 24 publications

References 10 publications

A bending N-Well ballast layout to improve ESD robustness in fully-silicided CMOS technology

A bending N-Well ballast layout to improve ESD robustness in fully-silicided CMOS technology

<title>ESD protection design for advanced CMOS</title>

Distributed ESD protection for high-speed integrated circuits

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