On the Switching Parameter Variation of Metal Oxide RRAM—Part II: Model Corroboration and Device Design Strategy

Yu, Shimeng; Guan, Xialing; Wong, H.-S. Philip

doi:10.1109/ted.2012.2184544

Cited by 203 publications

(121 citation statements)

References 23 publications

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“…This is just a compensating effect [7] of the aging mechanism. Physical justification of such effects can be found in [4,6]. We have simulated this effect and we observe a verification of such effects.…”

Section: Cycle-to Cycle Variabilitysupporting

confidence: 54%

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Reliability issues in RRAM ternary memories affected by variability and aging mechanisms

Rubio

Escudero

Pouyan

2017

2017 IEEE 23rd International Symposium on on-Line Testing and Robust System Design (IOLTS)

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Abstract-Resistive switching Random Access Memories (RRAM) are being considered as a promising alternative for conventional memories mainly due to their high speed, scalability, CMOS compatibility, Non-Volatile behavior (NVM), and consequent orientation to low power consumption. Advances in the RRAM technology as well as enhancement of the control of the cells are opening the use of these devices for multi-valued logic. But the cycle-to-cycle variability and the still reduced endurance are becoming serious limitations. This paper analyzes the impact of both mechanisms on 1T1R cells and suggests potential adaptive mechanisms to enlarge its lifetime.

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Section: Cycle-to Cycle Variabilitysupporting

confidence: 54%

“…This variable is the reset voltage, Vreset. It has been presented in [4] and [6] that the HRS distribution is strongly affected by Vreset. As Vreset increases the mean value of HRS resistance increases while the relative standard deviation decreases.…”

Section: Cycle-to Cycle Variabilitymentioning

confidence: 99%

Reliability issues in RRAM ternary memories affected by variability and aging mechanisms

Rubio

Escudero

Pouyan

2017

2017 IEEE 23rd International Symposium on on-Line Testing and Robust System Design (IOLTS)

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“…When the minimum criterion is considered, the average read window gain during cycling increases up to 37%. This represents once again a plus for the IFV scheme since it demonstrates its enhanced ability in Set/Reset tail bits (i.e., cells harder to be switched) reduction [24]. The read window closure due to endurance degradation [25] could be attributed to the impact of impurities in the metal-organic AVD precursor, in particular to carbon [26].…”

Section: Endurance Analysismentioning

confidence: 94%

Electrical characterization and modeling of pulse-based forming techniques in RRAM arrays

Grossi

Zambelli

Olivo

et al. 2016

Solid-State Electronics

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The forming process, which corresponds to the activation of the switching filament in Resistive Random Access Memory (RRAM) arrays, has a strong impact on the cells' performances. In this paper we characterize and compare different pulse forming techniques in terms of forming time, yield and cell-to-cell variability on 4 kbits RRAM arrays. Moreover, post-forming modeling during Reset operation of correctly working and over formed cells has been performed. An incremental form and verify technique, based on a sequence of trapezoidal waveforms with increasing voltages followed by a verify operation that terminates when the expected switching behavior has been achieved, showed the best results. This procedure narrows the post-forming current distribution whereas reducing the reset switching voltage and the operative current. These advantages materialize in a better control of the cell-to-cell variability and in an overall time and energy saving at the system level.

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“…As more rows M are added to the crossbar, the output voltage V out decreases as a result of the decrease in R ref , R Y , and thus R eq , as determined in (7), (8), and (10). While the output voltages of scenarios C and D in Table I are close to 0 even with a small number of rows, the output voltages of scenarios A and B go down quickly, lowering ΔV out and constraining V offset , as determined in (5).…”

Section: Circuit Analysis Of An M-by-n Arraymentioning

confidence: 99%

“…The unique properties of the memristor can be beneficial for many applications, such as threshold switch [3], dynamic load [4] and memory, which is considered the primary application for these devices. Resistive random-access memory [5][6][7][8][9][10][11] is one interesting type of memristive device [12]. Unlike standard nonvolatile memory cells such as Flash, resistive random-access memory can be smaller, vertically stacked (three-dimensional crossbar array structures [13,14]), with lower energy and lower read/write latency [15][16][17].…”

Section: Introductionmentioning

confidence: 99%

Analysis of the row grounding technique in a memristor‐based crossbar array

Dozortsev

Goldshtein

Kvatinsky

2017

Circuit Theory & Apps

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SUMMARYUsing memristive devices within a crossbar array could pave the way for memories with higher density and speed than state-of-the-art Flash memory, while maintaining relatively low energy. However, memristive crossbar arrays have great difficulty distinguishing logical states because of sneak path currents. The row grounding technique eliminates the sneak path effect, allowing reliable sampling of the memristor state.In this paper, we analyze the row grounding technique and propose several methods and constraints for the design of memristive crossbar arrays. When the row grounding technique is used for these arrays, our analysis shows that increasing the number of rows can help reduce read latency and energy, in contrast to the case of capacitive memory arrays. Simulation results confirm the theoretical analysis proposed in this paper.

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On the Switching Parameter Variation of Metal Oxide RRAM—Part II: Model Corroboration and Device Design Strategy

Cited by 203 publications

References 23 publications

Reliability issues in RRAM ternary memories affected by variability and aging mechanisms

Reliability issues in RRAM ternary memories affected by variability and aging mechanisms

Electrical characterization and modeling of pulse-based forming techniques in RRAM arrays

Analysis of the row grounding technique in a memristor‐based crossbar array

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