On the oxide thickness dependence of the time-dependent-dielectric-breakdown

Oussalah, Slimane; Nebel, Fabien

doi:10.1109/hkedm.1999.836404

Cited by 15 publications

(7 citation statements)

References 5 publications

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“…Now by putting the values of FIT 1 and FIT 2 from Equations (8) and (9) into Equation (7), MTTF of the NoCGuard router is given as MTTF NoCGuard_router = 10 9 2830 + 10 9 753.7 + 10 9 2830 + 753. 7 ≈ 1959185.95 hours…”

Section: • Xb Pipeline Stagementioning

confidence: 99%

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NoCGuard: A Reliable Network-on-Chip Router Architecture

et al. 2020

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Aggressive scaling in deep nanometer technology enables chip multiprocessor design facilitated by the communication-centric architecture provided by Network-on-Chip (NoC). At the same time, it brings considerable challenges in reliability because a fault in the network architecture severely impacts the performance of a system. To deal with these reliability challenges, this research proposed NoCGuard, a reconfigurable architecture designed to tolerate multiple permanent faults in each pipeline stage of the generic router. NoCGuard router architecture uses four highly reliable and low-cost fault-tolerant strategies. We exploited resource borrowing and double routing strategy for the routing computation stage, default winner strategy for the virtual channel allocation stage, runtime arbiter selection and default winner strategy for the switch allocation stage and multiple secondary bypass paths strategy for the crossbar stage. Unlike existing reliable router architectures, our architecture features less redundancy, more fault tolerance, and high reliability. Reliability comparison using Mean Time to Failure (MTTF) metric shows 5.53-time improvement in a lifetime and using Silicon Protection Factor (SPF), 22-time improvement, which is better than state-of-the-art reliable router architectures. Synthesis results using 15 nm and 45 nm technology library show that additional circuitry incurs an area overhead of 28.7% and 28% respectively. Latency analysis using synthetic, PARSEC and SPLASH-2 traffic shows minor increase in performance by 3.41%, 12% and 15% respectively while providing high reliability.Electronics 2020, 9, 342 2 of 22 design and has led to the evolution of on-chip interconnection network or network-on-chip (NoC) [3,4]. NoC architecture is a packet-based inter-connected network that separates communication from the computation. As it is different from the shared bus, it facilitates customization in terms of bandwidth, buffers size, and topology. It offers scalability without using long global wires. NoC infrastructure consists of routers and links that are used to deliver packets via layered protocol [5].The continuous improvement in process technology yields higher transistor density [1]. It makes transistors and links more vulnerable to different fault mechanisms [6,7]. A fault in a transistor may lead to erroneous computation. Open/short circuit in links, result in data corruption. Even single fault can paralyze the whole chip. Primarily, faults are classified into permanent and transient categories [8]. Permanent faults are also known as hard faults, apparent in the chip for a lifetime after their occurrence. They permanently affect the functionality of the chip. They are traditionally caused by open/short circuits in links, time-dependent-dielectric-breakdown (TDDB) [9], electro-migration (EM) [10], stress migration, negative-bias-temperature-instability (NBTI) [11], hot carrier injection [12] and thermal cycling [13]. On the other hand, transient faults, also known as soft errors, occur only for on...

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Section: • Xb Pipeline Stagementioning

confidence: 99%

“…The maximum number of faults the router tolerates is the sum of the maximum number of faults each pipeline stage tolerates. Based on the above analysis, the maximum number of faults NoCGuard router tolerates is calculated as sum [9,20,20,3] = 52 f aults…”

Section: Mdtf Estimation Of Nocguard Routermentioning

confidence: 99%

NoCGuard: A Reliable Network-on-Chip Router Architecture

et al. 2020

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“…The first is the increasing complexity of the fabrication process, which results in a higher rate of post-manufacturing faults. The second is the decreasing feature size of transistors, which causes hot carrier injection (HCI) [ 14 ], time-dependent dielectric breakdown (TDDB) [ 15 ], and negative-bias temperature instability (NBTI) [ 16 ]. Post-manufacturing faults are controlled by improving the fabrication process, whereas the effects of defects such as HCI, TDDB, and NBTI are not reversible.…”

Section: Introductionmentioning

confidence: 99%

Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things

Rashid

Baloch

Shafique

et al. 2020

Sensors

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Network-on-chip (NoC) architectures have become a popular communication platform for heterogeneous computing systems owing to their scalability and high performance. Aggressive technology scaling makes these architectures prone to both permanent and transient faults. This study focuses on the tolerance of a NoC router to permanent faults. A permanent fault in a NoC router severely impacts the performance of the entire network. Thus, it is necessary to incorporate component-level protection techniques in a router. In the proposed scheme, the input port utilizes a bypass path, virtual channel (VC) queuing, and VC closing strategies. Moreover, the routing computation stage utilizes spatial redundancy and double routing strategies, and the VC allocation stage utilizes spatial redundancy. The switch allocation stage utilizes run-time arbiter selection. The crossbar stage utilizes a triple bypass bus. The proposed router is highly fault-tolerant compared with the existing state-of-the-art fault-tolerant routers. The reliability of the proposed router is 7.98 times higher than that of the unprotected baseline router in terms of the mean-time-to-failure metric. The silicon protection factor metric is used to calculate the protection ability of the proposed router. Consequently, it is confirmed that the proposed router has a greater protection ability than the conventional fault-tolerant routers.

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“…are called permanent faults. Reasons of permanent faults are time-dependent dielectric breakdown (TDDB) [7], negatively biased temperature instability [8], hot carrier injection [9], and electro-migration [10]. The fault that lasts only for a few clock cycles and temporarily affects the operation of the circuit is called transient fault.…”

Section: Introductionmentioning

confidence: 99%

“…To find out the FIT, we use the Failure in Time Estimation Model proposed in Paluri and Louri [37] Lifetime modeling framework proposed by Shin et al [38] is utilized in this work. The value of FIT for a single field effect transistor (FET) which is produced by time dependent dielectric breakdown (TDDB) can be calculated by Equation 5 [7] FIT per FET = dutycycle × 10 9…”

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confidence: 99%

Defender: A Low Overhead and Efficient Fault-Tolerant Mechanism for Reliable on-Chip Router

2019

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The ever-shrinking size of a transistor has made Network on Chip (NoC) susceptible to faults. A single error in the NoC can disrupt the entire communication. In this paper, we introduce Defender, a fault-tolerant router architecture, that is capable of tolerating permanent faults in all the parts of the router. We intend to employ structural modifications in baseline router design to achieve fault tolerance. In Defender we provide the fault tolerance to the input ports and routing computation unit by grouping the neighboring ports together. Default winner strategy is used to provide fault resilience to the virtual channel arbiters and switch allocators. Multiple routes are provided to the crossbar to tolerate the faults. Defender provides improved fault tolerance to all stages of routers as compared to the currently prevailing fault tolerant router architectures. Reliability analysis using silicon protection factor (SPF) and Mean Time to Failure (MTTF) metrics confirms that our proposed design Defender is 10.78 times more reliable than baseline unprotected router and then the current state of the art architectures.INDEX TERMS Network-on-Chip, router architecture, permanent fault tolerance, silicon protection factor, mean time to failure.

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On the oxide thickness dependence of the time-dependent-dielectric-breakdown

Cited by 15 publications

References 5 publications

NoCGuard: A Reliable Network-on-Chip Router Architecture

NoCGuard: A Reliable Network-on-Chip Router Architecture

Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things

Defender: A Low Overhead and Efficient Fault-Tolerant Mechanism for Reliable on-Chip Router

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