Defender: A Low Overhead and Efficient Fault-Tolerant Mechanism for Reliable on-Chip Router

Baloch, Naveed Khan; Baig, Muhammad Iram; Daneshtalab, Masoud

doi:10.1109/access.2019.2944490

Cited by 9 publications

(9 citation statements)

References 45 publications

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“…It divides the process of fault tolerance into substages of detection, diagnosis, repair, and recovery. Baloch et al [39] present a defender method for a faulttolerant router. It is based on adding other components to deal with router faults.…”

Section: Noc Background and Related Workmentioning

confidence: 99%

Self-Healing Router Approach for High-Performance Network-on-Chip

Khalil

Eldash

Kumar

et al. 2021

IEEE Open J. Circuits Syst.

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Network-on-Chip (NoC) is used as the communication network in many applications that use multiple cores or Processing Elements (PEs). Routers play a crucial role as connectors since a faulty router can degrade the NoC's performance and cause miscommunication between the network's components. Thus a faulty router may cause the system to fail. To avoid failure in routers in NoCs, a novel self-healing technique is proposed. Self-healing serves to recover hardware faults, and it is defined as the ability of a system to recover from its faults without any external intervention. The proposed self-healing method is to heal faulty routers and their port buffers of faults as they occur. The proposed method uses the neighboring routers of a faulty router for computation. The data packet includes three bits for routing. A neighbor's active router updates these bits according to the destination of the packet. A self-healing block is added inside each router. The proposed method also covers faulty buffers, and it uses active buffers to store the packet of a faulty one. It has been implemented and tested using VHDL and Altera Arria 10 GX FPGA. It has been found to attain improved reliability and Mean Time to Failure (MTTF) at an area overhead of 27%. It has been tested for complex NoC structure, and the results show it is practical, scalable, stable, and robust.INDEX TERMS NoC, self-healing, hardware faults, fault tolerance, neural network, FPGA architecture.

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Section: Noc Background and Related Workmentioning

confidence: 99%

Self-Healing Router Approach for High-Performance Network-on-Chip

Khalil

Eldash

Kumar

et al. 2021

IEEE Open J. Circuits Syst.

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“…The organization of faulttolerant approaches based on redundancy has been discussed in [127]. Authors in [128] have presented a low cost and efficient fault-tolerant router design for reliable NoC. Techniques presented in this particular design can prevent the router from permanent faults.…”

Section: Fault Tolerance Application Mapping In Nocmentioning

confidence: 99%

Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs

et al. 2020

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Network-on-chip (NoC) is evolving as a better substitute for incorporating a large number of cores on a single system-on-chip (SoC). The dependency on multi-core systems to accomplish the highperformance constraints of composite embedded applications is on the rise. This leads to the realization of efficient mapping approaches for such complex applications. The significance of efficient application mapping approaches has increased ever since the embedded applications have become more complex and performance-oriented. This paper presents the detailed comparative analysis and categorization of application mapping approaches with current trends in NoC design implementation. These approaches target to improve the performance of the whole system by optimizing communication cost, energy, power consumption, and latency. Apart from the categorization of the discussed approaches, comparison of communication cost, power, energy, and latency of the NoC system carried out on real applications like VOPD and MPEG4. Moreover, the best technique identified in each category based on the evaluation of performance results. INDEX TERMS Network-on-Chip, application mapping, NoC design, VOPD, System-on-Chip. I. INTRODUCTION System-on-Chip (SoC) is an archetype for the design and implementation of on-chip circuits that can support multiple systems on a single chip. The ever-rising number of processing cores on a single chip has made the efficiency of onchip designs as one of the major aspects in evaluating the average performance of embedded SoC. To fulfill the performance needs and to provide flexibility in the designs the field of Network on Chip (NoC) has emerged that separates the communication from the computation. Many surveys [1]-[7] are published in general and textbooks are also available on the topic [8]-[10]. There is still a need to solve more advanced research problems in NoC. Application mapping on NoC architecture has a prominent place among all the research problems which can be arbitrated from the published The associate editor coordinating the review of this manuscript and approving it for publication was Eyuphan Bulut. papers and current trends. This survey assumes a textbooklevel acquaintance of NoC terminology. The aim is to provide a comprehensive overview of all the aspects of application mapping (task graph generation, scheduling, optimization techniques, simulation setup, and performance evaluation metrics). The organization of this survey is as follows; first, we provide the reader the need and overview of application mapping in NoC presented in Section I. A detailed review and calcification of application mapping techniques in NoCs are discussed in Section II. The current and latest trends in application mapping are summarized in Section III. In Section IV performance comparison and the points that can create the difference between these techniques are highlighted. Finally, Section VI concludes this paper. A. MOTIVATION AND SCOPE Mostly synthetic traffic patterns are used to imitate the functionalities of rea...

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“…The XBAR unit employs a double bypass bus strategy. In [ 31 ], the authors proposed the Defender router. It also tolerates faults in all the components of the router.…”

Section: Related Workmentioning

confidence: 99%

Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things

Rashid

Baloch

Shafique

et al. 2020

Sensors

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Network-on-chip (NoC) architectures have become a popular communication platform for heterogeneous computing systems owing to their scalability and high performance. Aggressive technology scaling makes these architectures prone to both permanent and transient faults. This study focuses on the tolerance of a NoC router to permanent faults. A permanent fault in a NoC router severely impacts the performance of the entire network. Thus, it is necessary to incorporate component-level protection techniques in a router. In the proposed scheme, the input port utilizes a bypass path, virtual channel (VC) queuing, and VC closing strategies. Moreover, the routing computation stage utilizes spatial redundancy and double routing strategies, and the VC allocation stage utilizes spatial redundancy. The switch allocation stage utilizes run-time arbiter selection. The crossbar stage utilizes a triple bypass bus. The proposed router is highly fault-tolerant compared with the existing state-of-the-art fault-tolerant routers. The reliability of the proposed router is 7.98 times higher than that of the unprotected baseline router in terms of the mean-time-to-failure metric. The silicon protection factor metric is used to calculate the protection ability of the proposed router. Consequently, it is confirmed that the proposed router has a greater protection ability than the conventional fault-tolerant routers.

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Defender: A Low Overhead and Efficient Fault-Tolerant Mechanism for Reliable on-Chip Router

Cited by 9 publications

References 45 publications

Self-Healing Router Approach for High-Performance Network-on-Chip

Self-Healing Router Approach for High-Performance Network-on-Chip

Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs

Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things

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