Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things

Abstract

Network-on-chip (NoC) architectures have become a popular communication platform for heterogeneous computing systems owing to their scalability and high performance. Aggressive technology scaling makes these architectures prone to both permanent and transient faults. This study focuses on the tolerance of a NoC router to permanent faults. A permanent fault in a NoC router severely impacts the performance of the entire network. Thus, it is necessary to incorporate component-level protection techniques in a router. In the proposed scheme, the input port utilizes a bypass path, virtual channel (VC) queuing, and VC closing strategies. Moreover, the routing computation stage utilizes spatial redundancy and double routing strategies, and the VC allocation stage utilizes spatial redundancy. The switch allocation stage utilizes run-time arbiter selection. The crossbar stage utilizes a triple bypass bus. The proposed router is highly fault-tolerant compared with the existing state-of-the-art fault-tolerant routers. The reliability of the proposed router is 7.98 times higher than that of the unprotected baseline router in terms of the mean-time-to-failure metric. The silicon protection factor metric is used to calculate the protection ability of the proposed router. Consequently, it is confirmed that the proposed router has a greater protection ability than the conventional fault-tolerant routers.

An Optimized Nature-Inspired Metaheuristic Algorithm for Application Mapping in 2D-NoC

“…In comparison to RDV, fault tolerance is also greater against the topology modifications. In [ 4 ], Rashid et al proposed a reliable on-chip network communication architecture by making some architectural improvements in the existing NoC routers’ designs. In [ 11 ], a router’s controllers design based on finite-state machine (FSM) is presented for the minimization of error propagation, aiming at low utilization of logical resources.…”

“…The router is a basic building block of the NoC architecture; a fault-resilient router architecture is necessary for reliable on-chip communication. The authors of [ 3 , 4 , 5 , 6 ] did some architectural modifications in the existing NoC routers designs to propose a reliable on-chip network communication infrastructure. A message passing technique is used for the exchange of data between IP cores.…”

Application Mapping Using Cuckoo Search Optimization With Lévy Flight for NoC-Based System

“…A fault tolerant router architecture design named as defender is presented in [3], which is capable of tolerating permanent faults in all the parts of the router. The authors in [4], [5], also presented modifications in the existing NoC routers designs to propose a reliable on-chip network communication infrastructure.…”

SB-Router: A Swapped Buffer Activated Low Latency Network-on-Chip Router

“…Multi-core processors use NoC to interconnect thousands of cores rather than shared buses or point-to-point interconnect wires [2]. Switch Allocation (SA) is used to assign output ports to input ports [3]. SA also makes sure that there is no conflict in the flit transit [4].…”