Network-on-chip (NoC) is evolving as a better substitute for incorporating a large number of cores on a single system-on-chip (SoC). The dependency on multi-core systems to accomplish the highperformance constraints of composite embedded applications is on the rise. This leads to the realization of efficient mapping approaches for such complex applications. The significance of efficient application mapping approaches has increased ever since the embedded applications have become more complex and performance-oriented. This paper presents the detailed comparative analysis and categorization of application mapping approaches with current trends in NoC design implementation. These approaches target to improve the performance of the whole system by optimizing communication cost, energy, power consumption, and latency. Apart from the categorization of the discussed approaches, comparison of communication cost, power, energy, and latency of the NoC system carried out on real applications like VOPD and MPEG4. Moreover, the best technique identified in each category based on the evaluation of performance results. INDEX TERMS Network-on-Chip, application mapping, NoC design, VOPD, System-on-Chip. I. INTRODUCTION System-on-Chip (SoC) is an archetype for the design and implementation of on-chip circuits that can support multiple systems on a single chip. The ever-rising number of processing cores on a single chip has made the efficiency of onchip designs as one of the major aspects in evaluating the average performance of embedded SoC. To fulfill the performance needs and to provide flexibility in the designs the field of Network on Chip (NoC) has emerged that separates the communication from the computation. Many surveys [1]-[7] are published in general and textbooks are also available on the topic [8]-[10]. There is still a need to solve more advanced research problems in NoC. Application mapping on NoC architecture has a prominent place among all the research problems which can be arbitrated from the published The associate editor coordinating the review of this manuscript and approving it for publication was Eyuphan Bulut. papers and current trends. This survey assumes a textbooklevel acquaintance of NoC terminology. The aim is to provide a comprehensive overview of all the aspects of application mapping (task graph generation, scheduling, optimization techniques, simulation setup, and performance evaluation metrics). The organization of this survey is as follows; first, we provide the reader the need and overview of application mapping in NoC presented in Section I. A detailed review and calcification of application mapping techniques in NoCs are discussed in Section II. The current and latest trends in application mapping are summarized in Section III. In Section IV performance comparison and the points that can create the difference between these techniques are highlighted. Finally, Section VI concludes this paper. A. MOTIVATION AND SCOPE Mostly synthetic traffic patterns are used to imitate the functionalities of rea...
Summary Soft errors in network‐on‐chip (NoC) such as single bit upsets and multibit upsets cause hazardous effects such as congestion, deadlock, livelock, and corruption of data. Error‐correcting codes (ECCs) are the best choices to handle these soft errors in links and memory buffers of NoC, which is the need of all modern systems, including internet of thing (IoT) edge devices. Many of these ECCs cannot correct both random and burst errors. Specific codes possess the correction and detection capability at the cost of an increase in area, latency, and energy. In this article, a coding technique is proposed by using a single error correction double error detection‐triple adjacent error correction‐six adjacent error detection (SEC‐DED‐TAEC‐6AED) (24,16) I5, that provides both random and burst error fault tolerance for NoC. The proposed technique decreases the area, energy, and latency cost of the whole NoC. It also reduces the area overhead to 173.41% and 117.91% compare to joint crosstalk avoidance multiple error correction (JCAMEC) and joint crosstalk multiple error correction (JMEC), respectively. Besides, the delay overhead of the proposed technique reduces to 4.2% and 91.97% compared with JCAMEC and JMEC, respectively. The simulation results show that the proposed code possesses an enhanced ability of error correction and detection with 3.5 times less redundant bits and a 30% fast code rate compared with JMEC and JCAMEC. Hence, the proposed scheme can effectively be used for detecting and correcting single and multiple bit errors for on‐chip communication.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.