On the Origin of Hole Valence Band Injection on GIFBE in PD SOI n-MOSFETs

ECS Solid State Letters

You

et al. 2015

This paper introduces a method to determine the located region of trap position by the analysis of three-level random telegraph signal (RTS) in partially-depleted silicon-on-insulator n-channel metal-oxide-semiconductor field-effect-transistors. For the cases of two traps, the average time at the 2 nd level ( τ 2 ) is composed of average emission time of one trap and average capture time of the other. Comparison and analysis of τ 2 curves varying with gate voltage in RTS measurements with and without interchanged source/drain can clarify the located regions of the two traps. Moreover, the simplified equations are also considered and used to confirm the trap positions.Silicon-on-insulator (SOI) MOSFETs have been attracted attention recently due to their lower power consumption, high speed, increased circuit packing density and absence of CMOS latch-up. In addition, due to their power management characteristics and ability to switch to an improved operation speed in large-scale devices, SOI MOSFETs, memory devices, 1-3 and thin-film transistors (TFTs) 4-6 can be integrated into mobile electronic products. However, the floating body effect and self-heating effect 7-9 are inherent disadvantages in SOI devices. When devices are scaled down to deep sub-micrometer, the random telegraph signal (RTS) becomes a major issue and influences the performance of MOSFETs. 10-13 The RTS phenomenon is commonly caused by a carrier that has been captured and emitted by an oxide trap. Although researches on lateral trap position determined by 2-level channel current RTS (2-RTS) have been previously reported, [13][14][15] there are few reports that study the trap position in multilevel RTS. In this work, the located regions of lateral trap position are analyzed by 3-level channel current RTS (3-RTS) with and without interchanged S/D (reverse and forward operations). Then, according to the Shockley-Read-Hall (SRH) model, the located regions of the oxide trap are clarified by the comparisons between the average times at the medium channel current ( τ 2 ), or so-called the 2 nd level, under forward and reverse operations. Furthermore, the simplified equations, which are based on the SRH model, are used to confirm these trap positions. ExperimentalThe PD SOI nMOSFETs used in this study were fabricated by SOI technology with a T-gate structure. The thickness of silicon film and buried oxide are 0.15 μm and 1 μm, respectively. The gate oxide with thickness of 100 Å was grown on silicon film with a channel doping concentration of about 1.3 × 10 18 cm −3 . In this paper, the device has dimension of width/length = 1 μm/0.35 μm. The RTS measurements were performed by an Agilent B1500A semiconductor device analyzer, an Agilent B1530A Waveform-Generator/FastMeasurement-Unit (WGFMU) and a Cascade Microtech M150 measurement platform. Results and DiscussionFigure 1 shows the V G dependence on drain current RTS (I D -RTS) from V G = 0.45 V to 0.75 V with V D = 50 mV for a period of 100 * Electrochemical Society Active Member. z E-mail: tcchang3708@gma...

mentioning

confidence: 99%

A Method to Determine the Located Region of Lateral Trap Position by Analysis of Three-Level Random Telegraph Signals in n-MOSFETs

Chen

ECS Solid State Letters

You

et al. 2015

“…To achieve high speed, low gate leakage current, and power consumption, the continuous scaling down of metal oxide semiconductor field electrical field transistors (MOSFETs) is driving toward using high-k dielectric. [10][11][12][13][14] However, charge trapping in high-k gate stacks remains a key reliability issue, since it causes threshold voltage (V TH ) shift and drive current degradation [15][16][17][18] due to the filling of pre-existing high-k bulk defects. [19][20][21] Additionally, the issue of charge trapping effect has been found to have a great impact on hot carrier degradation (HCD), since hot carriers tend to be injected into the high-k layer, especially in short channel devices.…”

mentioning

confidence: 99%

Electron-electron scattering-induced channel hot electron injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors with high-k/metal gate stacks

Tsai

Applied Physics Letters

Chen

et al. 2014

Self Cite

This work investigates electron-electron scattering (EES)-induced channel hot electron (CHE) injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors (n-MOSFETs) with high-k/metal gate stacks. Many groups have proposed new models (i.e., single-particle and multiple-particle process) to well explain the hot carrier degradation in nanoscale devices and all mechanisms focused on Si-H bond dissociation at the Si/SiO 2 interface. However, for high-k dielectric devices, experiment results show that the channel hot carrier trapping in the pre-existing high-k bulk defects is the main degradation mechanism. Therefore, we propose a model of EES-induced CHE injection to illustrate the trapping-dominant mechanism in nanoscale n-MOSFETs with high-k/metal gate stacks. V

“…To achieve high speed and light weight, the continuous scaling down of metal oxide semiconductor field electrical field transistors (MOSFETs) is driving conventional SiO 2 -based dielectric to be only a few atomic layers thick, leading to excessive gate leakage current and reliability issues. [6][7][8] To solve the leakage current problem, it is necessary to increase the physical thickness of the gate dielectric. One of the drawbacks of increasing the physical thickness, however, is that drive current will be decreased.…”

mentioning

confidence: 99%

Abnormal threshold voltage shift under hot carrier stress in Ti1−xNx/HfO2 p-channel metal-oxide-semiconductor field-effect transistors

Tsai

Journal of Applied Physics

et al. 2013

Self Cite

This work investigates the channel hot carrier (CHC) effect in HfO 2 /Ti 1Àx N x p-channel metal oxide semiconductor field effect transistors (p-MOSFETs). Generally, the subthreshold swing (S.S.) should increase during CHC stress (CHCS), since interface states will be generated near the drain side under high electric field due to drain voltage (V d). However, our experimental data indicate that S.S. has no evident change under CHCS, but threshold voltage (V th) shifts positively. This result can be attributed to hot carrier injected into high-k dielectric near the drain side. Meanwhile, it is surprising that such V th degradation is not observed in the saturation region during stress. Therefore, drain-induced-barrier-lowering (DIBL) as a result of CHC-induced electron trapping is proposed to explain the different V th behaviors in the linear and saturation regions. Additionally, the influence of different nitrogen concentrations in HfO 2 /Ti 1Àx N x p-MOSFETs on CHCS is also investigated in this work. Since nitrogen diffuses to SiO 2 /Si interface induced pre-N it occurring to degrades channel mobility during the annealing process, a device with more nitrogen shows slightly less impact ionization, leading to insignificant charge trapping-induced DIBL behavior. V