On the mechanism of current-transport in Cu/CdS/SnO2/In–Ga structures

A compare of electrical characteristics in Al/p-Si (MS) and Al/C20H12/p-Si (MPS) type diodes using current–voltage (I–V) and capacitance–voltage (C–V) measurements

“…On the other hand, ln(I)À ln(V) plot for D 2 diode have two distinct linear regions (region 1: À 2.5 VoVo À 0.002V and region 2: 0.6VoVo1.61V) and their slope were found as 3.70 and 1.62. It is clear that the current conduction, at low bias region (region 1) for both diodes show almost the ohmic behavior, that is, the current is directly proportional to applied bias voltage [37][38][39][40]. On the other hand, in the second region, for both diodes the I-V relation can be characterized by power law dependence.…”

“…In this case, the increase in the number of injected electrons causes filling up the traps and coming up the space charges [37]. For D 2 diode, at strong forward bias region (region 3), because of the strong electron injection, the electrons escape from the traps and contributes to space-charge-limited-current [36][37][38][39][40].…”

Electrical transport properties of an isolated CdS microrope composed of twisted nanowires

“…However, Kaiser et al fitted the same curve to the calculated behavior with fluctuation-assisted tunneling and thermal activation model, giving a good account of the feature of the I-V curve [16]. In addition, the electrical transport mechanism of nano-CdS has been discussed by various theories [17][18][19]. For example, the single CdS nanowire synthesized by aqueous chemical growth showed a high electrical conductivity of 0.82 S cm −1 at room temperature and a small band gap of 0.055 eV, and the resistance of the nanowire increased exponentially with decreasing temperature, namely, the temperature dependence of resistance followed the typical thermal activation model [17].…”

Ferroelectric Bi3.25La0.75Ti3O12 photodiode for solar cell applications

“…The deviation could be quantitatively explained by assuming specific distribution of nanometer scale patches of small regions with low barrier height (BH). In general, the performance of a diode depends on various factors such as the presence of the localized interface states (N ss ) at the metal/semiconductor interface, interface preparation process, inhomogeneous barrier heights and series resistance (R s ) [12][13][14][15][16][17]. Among these factors, the R s and interfacial layer are effective in the high bias region and N ss is effective in the low and moderate bias regions.…”