We have studied the mechanisms underlying the Cyclic / Deposition Etch (CDE) of Si with either SiH 4 or SiH 2 Cl 2 + HCl for the deposition steps and HCl for the etch steps. We have first shown that the high partial pressure HCl etch rate of poly-Si was several times higher than the one of mono-crystalline Si (factor of 3-4 above 700°Cfactor of up to 15 at 600°C). We have then demonstrated that at 650°C, 300 Torr, SiH 4 / HCl CDE processes were selective versus SiO 2 provided that high numbers of cycles were used. We have then assessed the feasibility of growing rather thick Si 1-y C y layers at 600°C, 300 Torr thanks to SiH 4 and SiCH 6 (for a future used as stressors in devices with recessed Sources and Drains (S/D)). High growth pressures promoted the incorporation of C in substitutional rather than in interstitials sites, resulting in flat, rather high crystalline quality 30 nm thick Si 1-y C y layers with [C] subst. up to 1.3%. We have then showed that 20 Torr, SiH 2 Cl 2 + HCl -based CDE processes enabled to selectively grow 85 -140 nm thick, high crystalline quality intrinsic or in-situ doped Si Raised S/Ds on each side of multi-bridge channel Field Effect Transistors (FET) with Si 3 N 4 internal spacers (T = 750°C for Si and Si:B, T = 800°C for Si:Ph). Finally, we have demonstrated the efficiency of 1 and 6 cycles CDE process (instead of a unique growth step) in suppressing mushrooming on top of un-capped poly-Si gates of Fully Depleted Silicon-On-Insulator FETs after the formation of Si RSD. {116}-{117} facets at the boundary between the gate stack and the S/D regions together with moat recess at the edges of active regions were however associated to our CDE processes.