On the Implementation of Time-Multiplexed Frequency-Response Masking Filters

Alam, Syed Asad; Gustafsson, Oscar

doi:10.1109/tsp.2016.2557298

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Multistage Frm Technique1

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Cited by 7 publications

(2 citation statements)

References 23 publications

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“…The implementation of FRM filters on hardware platforms such as field programmable gate array (FPGA) has been investigated in several articles [69][70][71][72][73]. Sev-…”

Section: Basic Principlementioning

confidence: 99%

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Design of recursive digital filters using frequency-response masking technique

Liu¹

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“…The implementation of FRM filters on hardware platforms such as field programmable gate array (FPGA) has been investigated in several articles [69][70][71][72][73]. Sev-…”

Section: Basic Principlementioning

confidence: 99%

“…In [70], a modified FRM filter suitable for FPGA implementation is proposed where the bandedge shaping filter is implemented using two to three cascaded short filters. Architectures for time-multiplexed FRM filters are introduced in [73].…”

Section: Multistage Frm Techniquementioning

confidence: 99%

Design of recursive digital filters using frequency-response masking technique

Liu¹

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Improved FRM-based maximally decimated filter bank with NTB for software radio channelizer

Zhang

et al. 2018

AEU - International Journal of Electronics and Communications

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Design of Vedic multiplierbased FIR filter for signal processing applications

Pasuluri

Sonti

2021

J. Phys.: Conf. Ser.

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Digital Signal Processing (DSP) devices are becoming increasingly important with the introduction of multiple signal processing techniques. Vedic Multiplier is one of the most common applications for high-speed DSP deployment. This paper constitutes a significant development in the design of the FIR filter architecture based on the modified Nikhalam Sutra Vedic multiplier. In addition, the Kongestone adder is used to increase speed performance. Using Xilinx FPGA Spartan 6 with Xilinx ISE, the modified architecture of FIR filter has been simulated and synthesized for achieving optimized results. The simulation results of the proposed FIR filter architecture illustrate that it operates at least 20 percent faster than traditional multiplier-based FIR filters

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On the Implementation of Time-Multiplexed Frequency-Response Masking Filters

Cited by 7 publications

References 23 publications

Design of recursive digital filters using frequency-response masking technique

Design of recursive digital filters using frequency-response masking technique

Improved FRM-based maximally decimated filter bank with NTB for software radio channelizer

Design of Vedic multiplierbased FIR filter for signal processing applications

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