On the exploitation of a high-throughput SHA-256 FPGA design for HMAC

Abstract

High-throughput and area-efficient designs of hash functions and corresponding mechanisms for Message Authentication Codes (MACs) are in high demand due to new security protocols that have arisen and call for security services in every transmitted data packet. For instance, IPv6 incorporates the IPSec protocol for secure data transmission. However, the IPSec's performance bottleneck is the HMAC mechanism which is responsible for authenticating the transmitted data. HMAC's performance bottleneck in its turn is the underlying hash function. In this article a high-throughput and small-size SHA-256 hash function FPGA design and the corresponding HMAC FPGA design is presented. Advanced optimization techniques have been deployed leading to a SHA-256 hashing core which performs more than 30% better, compared to the next better design. This improvement is achieved both in terms of throughput as well as in terms of throughput/area cost factor. It is the first reported SHA-256 hashing core that exceeds 11Gbps (after place and route in Xilinx Virtex 6 board).

Iso-X: A Flexible Architecture for Hardware-Managed Isolated Execution

“…For example, the SHA-256 hashing on a dedicated crypto-engine clocked at 170MHz requires 0.125 cycles/byte according to [32], which is about 10x faster than the software implementation reported in Table V. As another example, AES encryption performed on a separate engine clocked at 340MHz requires 0.69 cycles/byte [19], which is about 1.6x faster than encryption that uses Intel's AES-NI instructions.…”

Scan-based Side-channel Attack against HMAC-SHA-256 Circuits Based on Isolating Bit-transition Groups Using Scan Signatures

“…As below, we separately discuss other implementations of SHA-256 circuit and other implementations of HMAC-SHA-256 circuit. 6.1.1 Scan-based Attack against Other SHA-256 Circuit Implementations As far as we know, basic iterative SHA-256 circuit [29], [40], two-unrolled SHA-256 circuit [41], [42], pipelining SHA-256 circuit [43], [44], two-unrolled pipelining SHA-256 circuit [45], four-unrolled pipelining SHA-256 circuit [45], and compact SHA-256 circuit [46] are proposed as SHA-256 circuit implementations.…”

“…This implementation is the simplest and has a small area compared to Ref. [42]. However, there are other HMAC-SHA-256 circuit implementations that utilize two SHA-256 circuit blocks inside [42].…”

“…[42]. However, there are other HMAC-SHA-256 circuit implementations that utilize two SHA-256 circuit blocks inside [42]. Now, let SHA a and SHA b be the two SHA-256 circuit blocks in the HMAC-SHA-256 circuit.…”

“…For example, Ref. [42] proposes the HMAC-SHA-256 circuit implementation in this case. In this circuit implementation, when a message M is inserted into SHA a , only the message M which is dependent on M is inserted into SHA b .…”