A Configurable Implementation of the SHA-256 Hash Function

Martino, Raffaele; Cilardo, Alessandro

doi:10.1007/978-3-030-33509-0_52

Cited by 1 publication

(5 citation statements)

References 12 publications

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“…To ensure a fair comparison with other existing SHA-256 architectures, such as [18], [19], [20], [21], [22], and [23], we synthesized the proposed CME double SHA-256 circuit on four Xilinx FPGA boards, including Kintex UltraScale (XCKU5P-ffva676-3-e), Virtex 7(XC7VX1140T-FLG1926-2), Artix 7 (XC7A200T-FBG484-1), and Zynq UltraScale+ ZCU102 (XCZU9EG-FFVB1156-2-e).…”

Section: Fpga Experiments 1) Fpga Synthesis Resultsmentioning

confidence: 99%

“…The results are shown in Table 4. It is worth noting that the existing architectures in [18], [19], [20], [21], [22] and [23] are single SHA-256 architectures that must repeat the computation three times to generate a double SHA-256 hash value for Bitcoin mining. Thus, the number of clock cycles required to compute a double SHA-256 is tripled.…”

Section: Fpga Experiments 1) Fpga Synthesis Resultsmentioning

confidence: 99%

“…On the Kintex UltraScale FPGA, the hardware efficiency (Mbps/LUT) of the proposed CME double SHA-256 architecture is enhanced by 1,047% (9.52 vs. 0.83), 488% (9.52 vs. 1.62), and 7% (9.52 vs. 8.92) compared to the hardware efficiencies of the architectures in [18], [19], and [23], respectively. On the Virtex 7 FPGA, the hardware efficiency of the proposed architecture is enhanced by 7% (5.86 vs. 5.5), 762% (5.86 vs. 0.68), and 7% (5.86 vs. 5.48) compared to the the hardware efficiencies of the architectures in [20], [21], and [23], respectively.…”

Section: Fpga Experiments 1) Fpga Synthesis Resultsmentioning

confidence: 99%

“…8) is divided into three phases. Phase 1 includes CME2 4 to CME2 19 . Each operation requires a 128-bit register (or four 32-bit registers) to store and pipeline W 0 to W 3 .…”

Section: Cme Hardware Circuitsmentioning

confidence: 99%

“…The authors of [17] used a combination of techniques such as carry-save-adders and pipelines to increase the performance of SHA-256. Pipeline and unrolled techniques are presented in [18] and [19] to increase the throughput of SHA-256. The authors of [20]- [22] presented a SHA-256 implementation on an FPGA for performance evaluation, with no technique optimization.…”

Section: Introductionmentioning

confidence: 99%

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Double SHA-256 Hardware Architecture With Compact Message Expander for Bitcoin Mining

et al. 2020

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In the Bitcoin network, computing double SHA-256 values consumes most of the network energy. Therefore, reducing the power consumption and increasing the processing rate for the double SHA-256 algorithm is currently an important research trend. In this paper, we propose a high-data-rate low-power hardware architecture named the compact message expander (CME) double SHA-256. The CME double SHA-256 architecture combines resource sharing and fully unrolled datapath technologies to achieve both a high data rate and low power consumption. Notably, the CME algorithm utilizes the double SHA-256 input data characteristics to further reduce the hardware cost and power consumption. A review of the literature shows that the CME algorithm eliminates at least 9.68% of the 32-bit XOR gates, 16.49% of the 32-bit adders, and 16.79% of the registers required to calculate double SHA-256. We synthesized and laid out the CME double SHA-256 using CMOS 0.18 µm technology. The hardware cost of the synthesized circuit is approximately 13.88% less than that of the conventional approach. The chip layout size is 5.9mm×5.9mm, and the correctness of the circuit was verified on a real hardware platform (ZCU 102). The throughput of the proposed architecture is 61.44 Gbps on an ASIC with Rohm 180nm CMOS standard cell library and 340 Gbps on a FinFET FPGA 16nm Zynq UltraScale+ MPSoC ZCU102.

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Section: Fpga Experiments 1) Fpga Synthesis Resultsmentioning

confidence: 99%

Section: Fpga Experiments 1) Fpga Synthesis Resultsmentioning

confidence: 99%

Section: Fpga Experiments 1) Fpga Synthesis Resultsmentioning

confidence: 99%

“…8) is divided into three phases. Phase 1 includes CME2 4 to CME2 19 . Each operation requires a 128-bit register (or four 32-bit registers) to store and pipeline W 0 to W 3 .…”

Section: Cme Hardware Circuitsmentioning

confidence: 99%