On the crack and delamination risk optimization of a Si-interposer for LED packaging

Auersperg, J.; Dudek, R.; Jordan, R.; Bochow-Neß, O.; Rzepka, Sven; Michel, B.

doi:10.1016/j.microrel.2014.02.018

Cited by 8 publications

(2 citation statements)

References 11 publications

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“…18, right). Suitable dimension of the vias were calculated in advance [17]. The substrate wafer contains a large electrical isolated thermal pad on the bottom side and four die bond positions on the top.…”

Section: Processingmentioning

confidence: 99%

Advanced packaging methods for high-power LED modules

et al. 2015

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LED luminaires are already beyond retrofit systems, which are limited in heat dissipation due to the old fitting standards. Actual LED luminaries are based on new LED packages and modules. Heat dissipation through the first and second level interconnect is a key issue for a successful LED package. Therefore the impact of known bonding technologies as gluing and soldering and new technologies like sintering and transient liquid phase soldering were analyzed and compared. A realized hermetic high power LED package will be shown as example. The used new techniques result in a module extremely stable against further assembly processes and harsh operating conditions.

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Section: Processingmentioning

confidence: 99%

Advanced packaging methods for high-power LED modules

et al. 2015

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“…Given that chip-stacking packages, combined with either silicon-based or glass/ceramic-based interposers, are promising frameworks [ 1 , 2 , 3 , 4 , 5 ] for three-dimensional integrated circuit (3D-IC) integrations [ 6 , 7 , 8 ], microbump (μ-bump) reliability must be enhanced. Processes, such as chip grinding, position adjustment and planarity of assembly, the formation of through-silicon via (TSV), and the composition and dimensions of μ-bumps, should be emphasized to improve the functionality of 3D-IC packages.…”

Section: Introductionmentioning

confidence: 99%

Effect of Wafer Level Underfill on the Microbump Reliability of Ultrathin-Chip Stacking Type 3D-IC Assembly during Thermal Cycling Tests

Lee

2017

Materials

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The microbump (μ-bump) reliability of 3D integrated circuit (3D-IC) packaging must be enhanced, in consideration of the multi-chip assembly, during temperature cycling tests (TCT). This research proposes vehicle fabrications, experimental implements, and a nonlinear finite element analysis to systematically investigate the assembled packaging architecture that stacks four thin chips through the wafer level underfill (WLUF) process. The assembly of μ-bump interconnects by daisy chain design shows good quality. Results of both TCT data and the simulation indicate that μ-bumps with residual SnAg solders can reach more than 1200 fatigue life cycles. Moreover, several important design factors in the present 3D-IC package influence μ-bump reliability. Analytical results show that the μ-bump’s thermo-mechanical reliability can be improved by setting proper chip thickness, along with a WLUF that has a low elastic modulus and a small coefficient of thermal expansion.

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