2017
DOI: 10.3390/ma10101220
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Effect of Wafer Level Underfill on the Microbump Reliability of Ultrathin-Chip Stacking Type 3D-IC Assembly during Thermal Cycling Tests

Abstract: The microbump (μ-bump) reliability of 3D integrated circuit (3D-IC) packaging must be enhanced, in consideration of the multi-chip assembly, during temperature cycling tests (TCT). This research proposes vehicle fabrications, experimental implements, and a nonlinear finite element analysis to systematically investigate the assembled packaging architecture that stacks four thin chips through the wafer level underfill (WLUF) process. The assembly of μ-bump interconnects by daisy chain design shows good quality. … Show more

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Cited by 9 publications
(3 citation statements)
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“…Recently, electronic encapsulation and the development of underfill materials have attracted considerable interest in heat dissipation and have become the most cutting-edge approaches in this field. An ideal underfill material must not only have high thermal conductivity (TC) but also low coefficient of thermal expansion (CTE), as underfilling shields the die bumps from thermomechanical stress generated between the die and substrate or another die, thus improving the link strength of electrical junctions and compensating for the differences in thermal expansion between two connecting materials, which might lead to device malfunction [ 10 , 11 , 12 ].…”
Section: Introductionmentioning
confidence: 99%
“…Recently, electronic encapsulation and the development of underfill materials have attracted considerable interest in heat dissipation and have become the most cutting-edge approaches in this field. An ideal underfill material must not only have high thermal conductivity (TC) but also low coefficient of thermal expansion (CTE), as underfilling shields the die bumps from thermomechanical stress generated between the die and substrate or another die, thus improving the link strength of electrical junctions and compensating for the differences in thermal expansion between two connecting materials, which might lead to device malfunction [ 10 , 11 , 12 ].…”
Section: Introductionmentioning
confidence: 99%
“…Out of the demand to realize more wafers stacking layer-by-layer, wafer needs to be thinned from about 780 µm to less than 10 µm and be processed to the status with a demanding thickness uniformity [3]. For a better chip thermo-mechanical reliability, the wafer needs to be processed to a proper thickness [4]. Except the high surface accuracy and integrity [5][6][7], the process efficiency and thickness uniformity are the main requirements for wafer thinning technology.…”
Section: Introductionmentioning
confidence: 99%
“…There are 11 kinds of TC test condition [153], and they are listed in Table 2 internal force within a package. The internal force could provide the tension force or compression force to accelerate the package structure deformation [155][156][157][158][159]. The TC test temperature changes rapidly and the temperature range is large.…”
Section: Temperature Cycling Testmentioning
confidence: 99%