On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores

Abstract

Delay testing is mandatory for guaranteeing the correct behavior of today's high-performance microprocessors. Several methodologies have been proposed to tackle this issue resorting to additional hardware or to software self-test techniques. Software techniques are particularly promising as they resort to Assembly programs in normal mode of operation, without requiring circuit modifications; however, the problem of generating effective and efficient test programs for pathdelay fault detection is still open. This paper presents an innovative approach for the generation of path-delay self-test programs for microprocessors, based on an evolutionary algorithm and on ad-hoc software simulation/hardware emulation heuristic techniques. Experimental results show how the proposed methodology allows generating suitable test programs in reasonable times.

Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors

“…The obtained coverage values (Table I) are comparable to the ones obtained using other approaches [14] [19]. It must be noted that not-covered faults include functionally untestable ones, which do not determine the circuit performances and cannot be tested functionally.…”

“…It must be noted that not-covered faults include functionally untestable ones, which do not determine the circuit performances and cannot be tested functionally. The required time computation compares favorably with the time required in [19]. The experiments run on an Intel E6400 @2.13 GHz.…”

“…As a matter of fact, excitation conditions for faults belonging to the same structurally coherent fault group are likely to be stressed by the same instructions. Details on this topic can be found in [19].…”

“…For this task, during the RTL simulation of the test program execution, the values of the flip-flops feeding the investigated path are analyzed at each clock cycle in order to check for the excitation conditions (both on on-path and off-path); whenever they are met, a faulty value is forced on the path endpoint for one clock cycle (fault injection, [19]). From that point in time, the state of all flipflops is saved at each clock cycle and compared to the original (fault-free) simulation: if the simulation of the already generated program on the sabotaged RTL introduces a change on the processor output ports at any time following the fault injection, the test program achieves excitation and observation of the addressed fault and is complete.…”

“…For automatically generating test programs, the new implementation of an evolutionary algorithm addressing multiobjective optimization is employed. The main advantage introduced is the improvement in the flow performances compared to other approaches based only on gate-level simulation [19].…”