Standard cell libraries are an integral part of converting an RTL to a manufacturable physical design. The automatic place and route EDA tools use these characterized standard cell libraries to arrive at an optimal design within given constraints. The correlation between characterized data and the actual behaviour of cells on Silicon is critical for meeting the desired performance of the manufactured chip. In this paper, we present a modular design and measurement method which can be implemented in an ASIC for correlating the characteristics of the standard cell library. This method simplifies the design of the package and the test board and relatively simple test equipment can be used to measure the silicon characteristics. The ASIC presented in this paper was designed in 180nm for characterizing standard cells, which are delivered as part of the foundry design kit.