On performance of series connected CMOS vertical hall devices

Compensation of Assembly Tolerances in Magnetic Current Sensors with External Conductor

“…In [8], the performance of vertical Halls in series is analyzed. With such connections higher SNR and a lower residual offset and current consumption is achievable.…”

“…3. The difference signals defined by (6) and (8) are best to synthesize in the analog domain, using amplifiers preceding the A to D conversion. The linear combination of the vertical-and lateral difference signals in (9) and (13) shall be realized by a DSP, while the compensation-factor is a tunable EEPROM-parameter and fits the specific application layout.…”

Intrinsic limits of the sensitivity of CMOS integrated vertical Hall devices

“…The state of the art performances for CMOS integrated VHD are residual offset of about 400 T and resolution around 100 T over 1.6 kHz bandwidth [13,14]. On the way to an optimized CMOS integrated VHD, the uneven influence of junction field effect on the offset and on the sensitivity of the VHD has been recently studied in order to propose suitable biasing of the vertical structures [15]. In this paper we explain with the help of 2D FEM simulations why the lower sensitivity of a VHD is intrinsic to its structure.…”