2009
DOI: 10.1016/j.sna.2009.03.006
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Intrinsic limits of the sensitivity of CMOS integrated vertical Hall devices

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Cited by 37 publications
(15 citation statements)
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References 15 publications
(20 reference statements)
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“…However, in parallel-field Hall structures the current paths are curvilinear and the kinetic processes are such that in magnetic field B Hall potentials are generated on all boundary surfaces of the chip, inclusive on the rear side. As shown in [15], there is transfer of the Hall voltage from the rear side via the lateral boundaries to the top chip plane while the substrate depth increases. In the general case, the measured Hall voltage V H 1,2 (B) with two Hall terminals H 1 and H 2 located at the top substrate plane is always reduced with respect to the entire Hall voltage V Hall (B) generated in the parallel-field Hall microdevice, V H 1,2 (B) = KV Hall , where the coefficient K is substantially <1.…”
Section: Concept Of the Novel Two-axis Hall Devicementioning
confidence: 98%
See 3 more Smart Citations
“…However, in parallel-field Hall structures the current paths are curvilinear and the kinetic processes are such that in magnetic field B Hall potentials are generated on all boundary surfaces of the chip, inclusive on the rear side. As shown in [15], there is transfer of the Hall voltage from the rear side via the lateral boundaries to the top chip plane while the substrate depth increases. In the general case, the measured Hall voltage V H 1,2 (B) with two Hall terminals H 1 and H 2 located at the top substrate plane is always reduced with respect to the entire Hall voltage V Hall (B) generated in the parallel-field Hall microdevice, V H 1,2 (B) = KV Hall , where the coefficient K is substantially <1.…”
Section: Concept Of the Novel Two-axis Hall Devicementioning
confidence: 98%
“…The five-contact parallelfield Hall microsensors are found out to drastically reduce the internal 1/f noise by about three orders of magnitude since the biasing current does not flow through the Hall terminals [14]. Following from the numerous experimental results and the 2D FEM simulations and analysis carried out in [15], the shallower the CMOS parallel-field Hall device, the higher the short-circuit effect, and as a consequence, the magnetosensitivity and the signal-to-noise ratio will be reduced. As proven in [15] again, this microsensor class with two sensing contacts H 1 and H 2 are intrinsically limited in terms of measured transducer efficiency compared to the well-known Hall elements with orthogonal activation at equivalent doping level and thickness.…”
Section: Concept Of the Novel Two-axis Hall Devicementioning
confidence: 99%
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“…Les capteurs verticaux déve-loppés en technologie standard CMOS à cette occasion sont une réelle innovation technologique (Fig. 1b) [12][13][14][15].…”
Section: Développements Microélectroniquesunclassified