On overcoming the limitations of single-ended signaling for graphics memory interfaces

Amirkhany, Amir; Beyene, W.T.; Madden, Chris; Abbasfar, Aliazam; Secker, D.; Oh, Dan; Hekmat, Mohammad; Schmitt, R.; Yuan, Chuck

doi:10.1109/asscc.2011.6123655

Cited by 5 publications

(2 citation statements)

References 7 publications

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“…On the other hand, single-ended signaling is considered more pin efficient. Given the same pin count, the single-ended interface can operate at lower data rate per bit but still achieve the same aggregated bandwidth to meet the system requirement [1]. Modern high-end graphics systems need larger memory bandwidth but meanwhile have been close to or already reached the I/O density and thermal dissipation limit.…”

Section: Introductionmentioning

confidence: 98%

Modeling and measurement of supply noise induced jitter in a 12.8Gbps single-ended memory interface

Lan

Han

Schmitt

2012

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems

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Analyzing power supply noise characteristics and predicting its jitter impact is critical in designing the 12.8Gbps single-ended memory interface achieving better than 5mW/Gbps energy efficiency. The clocking circuit jitter performance is characterized by jitter sensitivity. The power supply noise induced jitter (PSIJ) is derived by combining the noise spectrum and sensitivity profile. The final PSIJ prediction matches closely with the on-chip measurement result.

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Section: Introductionmentioning

confidence: 98%

Modeling and measurement of supply noise induced jitter in a 12.8Gbps single-ended memory interface

Lan

Han

Schmitt

2012

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems

Self Cite

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“…Simulations were performed to analyze the transfer function of impact of crosstalk in multiple scenarios [5]. The key take-away from the simulation results in Figure 4 is the fact that particularly for the links that are analyzed in TBI II test system the impact of crosstalk is minimal when compared to commercial GDDR5 systems.…”

Section: B Crosstalk Analysis On Test Systemmentioning

confidence: 99%

Challenges in extending single-ended graphics memory data rates

Mukherjee

Vaidyanath

et al. 2012

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems

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While the need for higher graphics memory bandwidth continues to grow, it is evident that owing to the multitude of challenges in single ended signaling, pushing data rates beyond 6 Gbps is exceedingly difficult. To isolate, quantify and combat the most important factors that limit the performance of modern high speed single ended systems, a high speed GDDR5 memory system (link width: x32) has been designed using a Rambus prototype test-chip (TSMC 40 nm process node) and a leading single ended signaling graphics GDDR5 DRAM. Critical challenges faced in scaling the data rates up to 8 Gbps are presented and the varying impact of these challenges on the system margin is shown for increasing speeds. An example of a chip-to-chip system between two prototype test chips, that mitigates these performance limiting determinants, is shown to operate robustly at data rates beyond 8 Gbps. The ingredients of this system are likely techniques for the future graphics memories.

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The design of higher-order reference voltage generation circuits for single-ended memory interfaces

Beyene

2012

2012 IEEE 62nd Electronic Components and Technology Conference

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On overcoming the limitations of single-ended signaling for graphics memory interfaces

Cited by 5 publications

References 7 publications

Modeling and measurement of supply noise induced jitter in a 12.8Gbps single-ended memory interface

Modeling and measurement of supply noise induced jitter in a 12.8Gbps single-ended memory interface

Challenges in extending single-ended graphics memory data rates

The design of higher-order reference voltage generation circuits for single-ended memory interfaces

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