Challenges in extending single-ended graphics memory data rates

Abstract

While the need for higher graphics memory bandwidth continues to grow, it is evident that owing to the multitude of challenges in single ended signaling, pushing data rates beyond 6 Gbps is exceedingly difficult. To isolate, quantify and combat the most important factors that limit the performance of modern high speed single ended systems, a high speed GDDR5 memory system (link width: x32) has been designed using a Rambus prototype test-chip (TSMC 40 nm process node) and a leading single ended signaling graphics GDDR5 DRAM. Critical challenges faced in scaling the data rates up to 8 Gbps are presented and the varying impact of these challenges on the system margin is shown for increasing speeds. An example of a chip-to-chip system between two prototype test chips, that mitigates these performance limiting determinants, is shown to operate robustly at data rates beyond 8 Gbps. The ingredients of this system are likely techniques for the future graphics memories.